4.3.7. The Processor Feature Registers

There are two Processor Feature Registers, PFR0 and PFR1. This section describes:

c0, Processor Feature Register 0

The PFR0 characteristics are:

Purpose

Provides information about the execution state support and programmers model for the processor.

Usage constraints

PFR0 is:

  • a read-only register

  • accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

Figure 4.12 shows the PFR0 bit assignments.

Figure 4.12. PFR0 bit assignments

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Table 4.8 shows the PFR0 bit assignments.

Table 4.8. PFR0 bit assignments

Bits Name Function
[31:16]-

SBZ.

[15:12]State3

Indicates support for Thumb Execution Environment (ThumbEE).

0x0 = no support.

[11:8]State2

Indicates support for acceleration of execution environments in hardware or software.

0x1 = the processor supports acceleration of execution environments in software.

[7:4]State1

Indicates type of Thumb encoding that the processor supports.

0x3 = the processor supports Thumb encoding with all Thumb instructions.

[3:0]State0

Indicates support for ARM instruction set.

0x1 = the processor supports ARM instructions.


To access PFR0 read CP15 with:

MRC p15, 0, <Rd>, c0, c1, 0 ; Read PFR0

c0, Processor Feature Register 1

The PFR1 characteristics are:

Purpose

Provides information about the execution state support and programmers model for the processor.

Usage constraints

PFR1 is:

  • a read-only register

  • accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

Figure 4.13 shows the PFR1 bit assignments.

Figure 4.13. PFR1 bit assignments

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Table 4.9 shows the PFR1 bit assignments.

Table 4.9. PFR1 bit assignments

Bits

NameFunction
[31:12]-

SBZ.

[11:8]Microcontroller programmers model

Indicates support for Microcontroller programmers model:

0x0 = no support.

[7:4]Security extension

Indicates support for Security Extensions architecture:

0x0 = no support.

[3:0]ARMv4 programmers model

Indicates support for standard ARMv4 programmers model:

0x1 = the processor supports the ARMv4 model.


To access the PFR1 read CP15 with:

MRC p15, 0, <Rd>, c0, c1, 1 ; Read PFR1
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