4.3.26. c11, Slave Port Control Register

The Slave Port Control Register characteristics are:

Purpose
  • Enables or disables TCM access to the AXI slave port in Privileged or User mode.

  • Enables access to the cache RAMs through the AXI slave port. See c1, Auxiliary Control Register.

Usage constraints

The Slave Port Control Register is:

  • a read/write register

  • accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

Figure 4.43 shows the Slave Port Control Register bit assignments.

Figure 4.43. Slave Port Control Register bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 4.45 shows the Slave Port Control Register bit assignments

Table 4.45. Slave Port Control Register bit assignments

Bits Name Function
[31:2]-RAZ/UNP.
[1]Privileged access

Defines level of access for TCM accesses:

0 = Non-privileged and privileged access, reset value

1 = Privileged access only.

[0]AXI slave enable

Enables or disables the AXI slave port for TCM accesses:

0 = Enables AXI slave port, reset value

1 = Disables AXI slave port.


To access the Slave Port Control Register, read or write CP15 with:

MRC p15, 0, <Rd>, c11, c0, 0 ; Read Slave Port Control Register
MCR p15, 0, <Rd>, c11, c0, 0 ; Write Slave Port Control Register
Copyright © 2010-2011 ARM. All rights reserved.ARM DDI 0460C
Non-ConfidentialID021511