6.3.6. c9, Performance Counter Selection Register

The PMSELR Register characteristics are:

  • selects an Event Count Register.

  • determines which count register is accessed or controlled by accesses to the Event Selection Register and the Event Count Register.

Usage constraints

The PMSELR Register is:

  • A read/write register.

  • Accessible in:


Available in all processor configurations.


Figure 6.6 shows the bit assignments.

Figure 6.6. PMSELR Register bit assignments

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Table 6.7 shows the bit assignments.

Table 6.7. PMSELR Register bit assignments




RAZ on reads, SBZP on writes



Counter select:

b00000 = selects counter 0

b00001 = selects counter 1

b00010 = selects counter 2.

Any values programmed in the PMSELR Register other than those specified in Table 6.7 are Unpredictable.

To access the PMSELR Register, read or write CP15 with:

MRC p15, 0, <Rd>, c9, c12, 5 ; Read  PMSELR Register
MCR p15, 0, <Rd>, c9, c12, 5 ; Write PMSELR Register
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