Cortex-R5 and Cortex-R5F Technical Reference Manual: 4.3.10. Memory Model Feature Registers

4.3.10. Memory Model Feature Registers

There are four Memory Model Feature Registers, MMFR0 to MMFR3. They are described in the following subsections:

c0, Memory Model Feature Register 0

The ID_MMFR0 characteristics are:

Purpose

The ID_MMFR0 provides information about the memory model, memory management, and cache support operations of the processor.

Usage constraints

The ID_MMFR0 is:

a read-only register
accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

See Table 4.11.

Figure 4.15 shows the ID_MMFR0 bit assignments.

Figure 4.15. ID_MMFR0 bit assignments

Table 4.11 shows the ID_MMFR0 bit assignments.

Table 4.11. ID_MMFR0 bit assignments

Bits	Name	Function
[31:28]	Innermost shareability	Indicates the innermost shareability domain implemented. RAZ/Unknown because only one shareability domain is implemented, see [15:12].
[27:24]	FCSE	Indicates support for Fast Context Switch Extension (FCSE). `0x0` = no support.
[23:20]	Auxiliary Registers	Indicates support for the auxiliary registers. `0x2` = the processor supports the Auxiliary Instruction and Data Fault Status Registers (AIFSR and ADFSR) and the Auxiliary Control Register.
[19:16]	TCM support	Indicates support for TCM and associated DMA. `0x1` = implementation defined.
[15:12]	Shareability levels	Indicates the number of shareability levels implemented. `0x0` = one level of shareability implemented
[11:8]	Outermost shareability	Indicates the outermost shareability domain implemented. `0x0` = implemented as non-cacheable
[7:4]	PMSA	Indicates support for Physical Memory System Architecture (PMSA). `0x3` = the processor supports PMSAv7 (subsection support).
[3:0]	VMSA	Indicates support for Virtual Memory System Architecture (VMSA). `0x0` = no support.

To access the ID_MMFR0 read CP15 with:

MRC p15, 0, <Rd>, c0, c1, 4 ; Read ID_MMFR0

c0, Memory Model Feature Register 1

The ID_MMFR1 Register characteristics are:

Purpose

Provides information about the memory model, memory management, and cache support of the processor.

Usage constraints

The ID_MMFR1 is:

a read-only register
accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

See Table 4.12.

Figure 4.16 shows the ID_MMFR1 bit assignments.

Figure 4.16. ID_MMFR1 bit assignments

Table 4.12 shows the ID_MMFR1 bit assignments.

Table 4.12. ID_MMFR1 bit assignments

Bits	Name	Function
[31:28]	Branch predictor	Indicates Branch Predictor management requirements. `0x0` = no MMU present.
[27:24]	L1 test clean operations	Indicates support for test and clean operations on data cache, Harvard or unified architecture. `0x0` = no support.
[23:20]	L1 cache maintenance operations (unified)	Indicates support for L1 cache, entire cache maintenance operations, unified architecture. `0x0` = no support.
[19:16]	L1 cache maintenance operations (Harvard)	Indicates support for L1 cache, entire cache maintenance operations, Harvard architecture. `0x0` = no support.
[15:12]	L1 cache line maintenance operations - Set and Way (unified)	Indicates support for L1 cache line maintenance operations by Set and Way, unified architecture. `0x0` = no support.
[11:8]	L1 cache line maintenance operations - Set and Way (Harvard)	Indicates support for L1 cache line maintenance operations by Set and Way, Harvard architecture. `0x0` = no support.
[7:4]	L1 cache line maintenance operations - MVA (unified)	Indicates support for L1 cache line maintenance operations by address, unified architecture. `0x0` = no support.
[3:0]	L1 cache line maintenance operations - MVA (Harvard)	Indicates support for L1 cache line maintenance operations by address, Harvard architecture. `0x0` = no support.

To access the ID_MMFR1 read CP15 with:

MRC p15, 0, <Rd>, c0, c1, 5 ; Read ID_MMFR1

c0, Memory Model Feature Register 2

The ID_MMFR2 characteristics are:

Purpose

The ID_MMFR2 provides information about the memory model, memory management, and cache support operations of the processor.

Usage constraints

The ID_MMFR2 is:

a read-only register
accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

See Table 4.13.

Figure 4.17 shows the ID_MMFR2 bit assignments.

Figure 4.17. ID_MMFR2 bit assignments

Table 4.13 shows the ID_MMFR2 bit assignments.

Table 4.13. ID_MMFR2 bit assignments

Bits	Name	Function
[31:28]	Hardware access flag	Indicates support for Hardware Access Flag. `0x0` = no support.
[27:24]	WFI	Indicates support for Wait-For-Interrupt stalling. `0x1` = the processor supports Wait-For-Interrupt.
[23:20]	Memory barrier	Indicates support for memory barrier operations. `0x2`, = he processor supports: DSB (formerly DWB) ISB (formerly Prefetch Flush) DMB.
[19:16]	TLB maintenance operations (unified)	Indicates support for TLB maintenance operations, unified architecture. `0x0` = no support.
[15:12]	TLB maintenance operations (Harvard)	Indicates support for TLB maintenance operations, Harvard architecture. `0x0` = no support.
[11:8]	L1 cache maintenance range operations (Harvard)	Indicates support for cache maintenance range operations, Harvard architecture. `0x0` = no support.
[7:4]	L1 background prefetch cache operations	Indicates support for background prefetch cache range operations, Harvard architecture. `0x0` = no support.
[3:0]	L1 foreground prefetch cache operations	Indicates support for foreground prefetch cache range operations, Harvard architecture. `0x0` = no support.

To access the ID_MMFR2 read CP15 with:

MRC p15, 0, <Rd>, c0, c1, 6 ; Read ID_MMFR2

c0, Memory Model Feature Register 3, MMFR3

The ID_MMFR3 characteristics are:

Purpose

Provides information about the two cache line maintenance operations for the processor.

Usage constraints

The ID_MMFR3 is:

a read-only register
accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

See Table 4.14.

Figure 4.18 shows the ID_MMFR3 bit assignments.

Figure 4.18. ID_MMFR3 bit assignments

Table 4.14 shows the ID_MMFR3 bit assignments.

Table 4.14. ID_MMFR3 bit assignments

Bits	Name	Function
[31:28]	Supersection support	RAZ because this is a PMSA implementation.
[27:24]	-	SBZ
[23:20]	Coherent walk	RAZ because this is a PMSA implementation.
[19:16]	-	SBZ
[15:12]	Maintenance broadcast	Indicates whether cache maintenance operations are broadcast. `0x0` = cache maintenance operations only affect local structures.
[11:8]	Branch predictor maintenance operations	Indicates support for branch predictor maintenance operations in systems with hierarchical cache maintenance operations. `0x2` = supports invalidate entire branch predictor array and invalidate branch predictor by MVA^[a].
[7:4]	Hierarchical cache maintenance operations by Set and Way	Indicates support for hierarchical cache maintenance operations by Set and Way. `0x1` = the processor supports invalidate cache, clean and invalidate, and clean by Set and Way.
[3:0]	Hierarchical cache maintenance operations by MVA	Indicates support for hierarchical cache maintenance operations by address. `0x1` = the processor supports: Invalidate data cache by address Clean data cache by address Clean and invalidate data cache by address Invalidate instruction cache by address Invalidate all instruction cache entries.
^[a]Both of these operations are NOP on Cortex-R5.

To access the ID_MMFR3 read CP15 with:

MRC p15, 0, <Rd>, c0, c1, 7 ; Read ID_MMFR3

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