Cortex-R5 and Cortex-R5F Technical Reference Manual: 4.3.17. c1, Auxiliary Control Register

4.3.17. c1, Auxiliary Control Register

The ACTLR characteristics are:

Purpose

Controls:

branch prediction
performance features
error and parity logic.

Usage constraints

The ACTLR is:

A read/write register.
Accessible in Privileged mode only.
ARM recommends that any instruction that changes bits [31:28] or [7] is followed by an ISB instruction to ensure that the changes have taken effect before any dependent instructions are executed.

Configurations

Available in all processor configurations.

Attributes

See Table 4.25.

Figure 4.28 shows the ACTLR bit assignments.

Figure 4.28. ACTLR bit assignments

Table 4.25 shows the ACTLR bit assignments.

Table 4.25. ACTLR bit assignments

Bits	Name	Function
[31]	DICDI^[a]	Case C dual issue control: 0 = Enabled. This is the reset value. 1 = Disabled.
[30]	DIB2DI^[a]	Case B2 dual issue control: 0 = Enabled. This is the reset value. 1 = Disabled.
[29]	DIB1DI^[a]	Case B1 dual issue control: 0 = Enabled. This is the reset value. 1 = Disabled.
[28]	DIADI^[a]	Case A dual issue control: 0 = Enabled. This is the reset value. 1 = Disabled.
[27]	B1TCMPCEN	B1TCM ECC check enable: 0 = Disabled 1 = Enabled. The primary input PARECCENRAMm[2]^[b] defines the reset value. If the BTCM is configured with ECC, you must always set this bit to the same value as B0TCMPCEN.
[26]	B0TCMPCEN	B0TCM ECC check enable: 0 = Disabled 1 = Enabled. The primary input PARECCENRAMm[1]^[b] defines the reset value. If the BTCM is configured with ECC, you must always set this bit to the same value as B1TCMPCEN.
[25]	ATCMPCEN	ATCM ECC check enable: 0 = Disabled 1 = Enabled. The primary input PARECCENRAMm[0]^[b] defines the reset value.
[24]	AXISCEN	AXI slave cache RAM access enable: 0 = Disabled. This is the reset value. 1 = Enabled. Note When AXI slave cache access is enabled, the caches are disabled and the processor cannot run any cache maintenance operations. If the processor attempts a cache maintenance operation, an Undefined Instruction exception is taken.
[23]	AXISCUEN	AXI slave cache RAM non-privileged access enable: 0 = Disabled. This is the reset value. 1 = Enabled.
[22]	DILSM	Disable Low Interrupt Latency (LIL) on load/store multiples: 0 = Enable LIL on load/store multiples. This is the reset value. 1 = Disable LIL on all load/store multiples.
[21]	DEOLP	Disable end of loop prediction: 0 = Enable loop prediction. This is the reset value. 1 = Disable loop prediction.
[20]	DBHE	Disable Branch History (BH) extension: 0 = Enable the extension. This is the reset value. 1 = Disable the extension.
[19]	FRCDIS	Fetch rate control disable: 0 = Normal fetch rate control operation. This is the reset value. 1 = Fetch rate control disabled.
[18]	-	SBZ.
[17]	RSDIS	Return stack disable: 0 = Normal return stack operation. This is the reset value. 1 = Return stack disabled.
[16:15]	BP	This field controls the branch prediction policy: b00 = Normal operation. This is the reset value. b01 = Branch always taken and history table updates disabled. b10 = Branch always not taken and history table updates disabled. b11 = Reserved. Behavior is Unpredictable if this field is set to b11.
[14]	DBWR	Disable write burst in the AXI master: 0 = Normal operation. This is the reset value. 1 = Disable write burst optimization.
[13]	DLFO	Disable linefill optimization in the AXI master: 0 = Normal operation. This is the reset value. 1 = Limits the number of outstanding data linefills to two.
[12]	ERPEG^[c]	Enable random parity error generation: 0 = Random parity error generation disabled. This is the reset value. 1 = Enable random parity error generation in the cache RAMs. Note This bit controls error generation logic during system validation. A synthesized ASIC typically does not have such models and this bit is therefore redundant for ASICs.
[11]	DNCH	Disable data forwarding for Non-cacheable accesses in the AXI master: 0 = Normal operation. This is the reset value. 1 = Disable data forwarding for Non-cacheable accesses.
[10]	FORA	Force outer read allocate (ORA) for outer write allocate (OWA) regions: 0 = No forcing of ORA. This is the reset value. 1 = ORA forced for OWA regions.
[9]	FWT	Force write-through (WT) for write-back (WB) regions: 0 = No forcing of WT. This is the reset value. 1 = WT forced for WB regions.
[8]	FDSnS	Force D-side to not-shared when MPU is off: 0 = Normal operation. This is the reset value. 1 = D-side normal Non-cacheable forced to Non-shared when MPU is off.
[7]	sMOV	sMOV of a divide does not complete out of order. No other instruction is issued until the divide is finished. 0 = Normal operation. This is the reset value. 1 = sMOV out of order disabled.
[6]	DILS	Disable low interrupt latency on all load/store instructions. 0 = Enable LIL on all load/store instructions. This is the reset value. 1 = Disable LIL on all load/store instructions.
[5:3]	CEC	Cache error control for cache parity and ECC errors. See Table 8.2 and Table 8.3 for more information about how these bits are used. The reset value is b100.
[2]	B1TCMECEN	B1TCM external error enable: 0 = Disabled 1 = Enabled. The primary input ERRENRAMm[2] defines the reset value.
[1]	B0TCMECEN	B0TCM external error enable: 0 = Disabled 1 = Enabled. The primary input ERRENRAMm[1] defines the reset value.
[0]	ATCMECEN	ATCM external error enable: 0 = Disabled 1 = Enabled. The primary input ERRENRAMm[0] defines the reset value.
^[a]See Dual issue ^[b]See Configuration signals. ^[c]This bit is only supported if parity error generation is implemented in your design.

To access the ACTLR, read or write CP15 with:

MRC p15, 0, <Rd>, c1, c0, 1 ; Read ACTLR

MCR p15, 0, <Rd>, c1, c0, 1 ; Write ACTLR

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4.3.17. c1, Auxiliary Control Register

Note

Note