6.3.4. c9, Overflow Flag Status Register

The PMOVSR Register characteristics are:


Indicates if event counters have overflowed. All overflow flags are reset to zero.

Usage constraints

The PMOVSR Register is accessible in:


Available in all processor configurations.


Figure 6.4 shows the bit assignments.

Figure 6.4. PMOVSR Register bit assignments

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Table 6.5 shows the bit assignments.

Table 6.5. PMOVSR Register bit assignments



Cycle counter overflow

Cycle counter overflow flag



UNP on reads, SBZP on writes



Counter 2 overflow flag



Counter 1 overflow flag



Counter 0 overflow flag

To access the PMOVSR Register, read or write CP15 with:

MRC p15, 0, <Rd>, c9, c12, 3 ; Read PMOVSR Register
MCR p15, 0, <Rd>, c9, c12, 3 ; Write PMOVSR Register

If an overflow flag is set to 1 in the PMOVSR register it remains set until one of the following happens:

The following operations do not clear the overflow flags:

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