Cortex-R5 and Cortex-R5F Technical Reference Manual: 4.1.2. MPU control and configuration

4.1.2. MPU control and configuration

The MPU control and configuration registers:

control program access to memory
designate areas of memory as either:
- Normal, Non-cacheable
- Normal, Cacheable
- Device
- Strongly Ordered.
detect MPU faults and external aborts.

The MPU control and configuration registers consist of one read-only register and 11 read/write registers. Figure 4.2 shows the arrangement of registers in this functional group.

Figure 4.2. MPU control and configuration registers

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