Cortex-R5 and Cortex-R5F Technical Reference ManualRevision: r1p1
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4.3.8. c0, Debug Feature Register 0

The ID_DFR0 characteristics are:

Purpose

Provides information about the debug system for the processor.

Usage constraints

ID_DFR0 is:

  • a read-only register

  • accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

See Table 4.10.

Figure 4.14 shows the ID_DFR0 bit assignments.

Figure 4.14. ID_DFR0 bit assignments

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Table 4.10 shows the ID_DFR0 bit assignments.

Table 4.10. ID_DFR0 bit assignments

Bits

NameFunction
[31:24]-

SBZ.

[23:20]

Microcontroller Debug model - memory mapped

Indicates support for the microcontroller debug model - memory mapped:

0x0 = no support.

[19:16]Trace debug model - memory mapped

Indicates support for the trace debug model - memory mapped:

0x1 = trace supported, memory mapped access.

[15:12]Trace debug model - coprocessor

Indicates support for the trace debug model - coprocessor:

0x0 = no support.

[11:8]Core debug model - memory mapped

Indicates the type of embedded processor debug model that the processor supports:

0x4 = ARMv7 based model - memory mapped.

[7:4]Secure debug model

Indicates the type of secure debug model that the processor supports:

0x0 = no support.

[3:0]Core debug model - coprocessor

Indicates the type of applications processor debug model that the processor supports:

0x0 = no support.


To access the ID_DFR0 read CP15 with:

MRC p15, 0, <Rd>, c0, c1, 2 ; Read ID_DFR0
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