6.3.12. c9, Interrupt Enable Clear Register

The PMINTENCLR Register characteristics are:


Determines if any of the PMXEVCNTR Registers, PMXEVCNTR0-PMXEVCNTR2 and PMCCNTR, generate an interrupt request on overflow.

Usage constraints

The PMINTENCLR Register is:

  • a read/write register

  • accessible in Privileged mode only.


Available in all processor configurations.


Figure 6.10 shows the bit assignments.

Figure 6.10. PMINTENCLR Register bit assignments

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Table 6.11 shows the bit assignments.

Table 6.11. PMINTENCLR Register bit assignments


PMCCNTR overflow interrupt

[30:3]ReservedUNP on reads, SBZP on writes
[2]P2PMXEVCNTR2 overflow interrupt
[1]P1PMXEVCNTR1 overflow interrupt
[0]P0PMXEVCNTR0 overflow interrupt

Reading this register returns the current setting, with a 1 in one of the counter bits indicating that interrupts are enabled for that counter. Writing a 1 to a particular interrupt disable bit disables interrupt generation on overflow of that counter. Writing a 0 has no effect. You can only enable interrupt requests by writing to the PMINTENSET Register.

To access the PMINTENCLR Register, read or write CP15 with:

MRC p15, 0, <Rd>, c9, c14, 2 ; Read PMINTENCLR Register
MCR p15, 0, <Rd>, c9, c14, 2 ; Write PMINTENCLR Register
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