4.3.18. c15, Secondary Auxiliary Control Register

The Secondary Auxiliary Control Register characteristics are:

Purpose

Controls:

  • branch prediction

  • performance features

  • error and parity logic.

Usage constraints

The Secondary Auxiliary Control Register is:

  • A read/write register.

  • Accessible in Privileged mode only.

  • ARM recommends that any instruction that changes bits [20:16] is followed by an ISB instruction to ensure that the changes have taken effect before any dependent instructions are executed.

Configurations

Available in all processor configurations.

Attributes

Figure 4.29 shows the Secondary Auxiliary Control Register bit assignments.

Figure 4.29. Secondary Auxiliary Control Register bit assignments

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Table 4.26 shows the Secondary Auxiliary Control Register bit assignments.

Table 4.26. Secondary Auxiliary Control Register bit assignments

BitsNameFunction
[31:23]-SBZ.
[22] DCHE

Disable hard-error support in the caches.[a]

0 = Enabled. The cache logic recovers from some hard errors.

1 = Disabled. Most hard errors in the caches are fatal. This is the reset value.

See Hard errors for more information.

[21]DR2B[b]

Enable random 2-bit error generation in cache RAMs. This bit has no effect unless ECC is configured, see Configurable options.

0 = Disabled. This is the reset value.

1 = Enabled.

Note

This bit controls error generation logic during system validation. A synthesized ASIC typically does not have such models and this bit is therefore redundant for ASICs.

[20]DF6DI

F6 dual issue control.[c]

0 = Enabled. This is the reset value.

1 = Disabled.

[19]DF2DI

F2_Id/F2_st/F2D dual issue control.[c]

0 = Enabled. This is the reset value.

1 = Disabled.

[18]DDI

F1/F3/F4dual issue control.[c]

0 = Enabled. This is the reset value.

1 = Disabled.

[17]DOODPFP

Out-of-order double-precision floating point instruction control.[c]

0 = Enabled. This is the reset value.

1 = Disabled.

[16]DOOFMACS

Out-of-order FMACS control.[c]

0 = Enabled. This is the reset value.

1 = Disabled.

[15:14]-SBZ.
[13]IXC

Floating-point inexact exception output mask.[c]

0 = Mask floating-point inexact exception output. The output FPIXCm is forced to zero. This is the reset value.

1 = Propagate floating point inexact exception flag FPSCR.IXC to output FPIXCm.

[12]OFC

Floating-point overflow exception output mask.[c]

0 = Mask floating-point overflow exception output. The output FPOFCm is forced to zero. This is the reset value.

1 = Propagate floating-point overflow exception flag FPSCR.OFC to output FPOFCm.

[11]UFC

Floating-point underflow exception output mask.[c]

0 = Mask floating-point underflow exception output. The output FPUFCm is forced to zero. This is the reset value.

1 = Propagate floating-point underflow exception flag FPSCR.UFC to output FPUFCm.

[10]IOC

Floating-point invalid operation exception output mask.[c]

0 = Mask floating-point invalid operation exception output. The output FPIOCm is forced to zero. This is the reset value.

1 = Propagate floating-point invalid operation exception flag FPSCR.IOC to output FPIOCm.

[9]DZC

Floating-point divide-by-zero exception output mask.[c]

0 = Mask floating-point divide-by-zero exception output. The output FPDZCm is forced to zero. This is the reset value.

1 = Propagate floating-point divide-by-zero exception flag FPSCR.DZC to output FPDZCm.

[8]IDC

Floating-point input denormal exception output mask.[c]

0 = Mask floating-point input denormal exception output. The output FPIDCm is forced to zero. This is the reset value.

1 = Propagate floating-point input denormal exception flag FPSCR.IDC to output FPIDCm.

[7:4]-SBZ.
[3]BTCMECC

Correction for internal ECC logic on BTCM ports.[d]

0 = Enabled. This is the reset value.

1 = Disabled.

[2]ATCMECC

Correction for internal ECC logic on ATCM port.[d]

0 = Enabled. This is the reset value.

1 = Disabled.

[1]BTCMRMW

Enables 64-bit stores for the BTCMs. When enabled, the processor uses read-modify-write to ensure that all reads and writes presented on the BTCM ports are 64 bits wide.[e]

0 = Disabled

1 = Enabled.

The primary input RMWENRAMm[1] defines the reset value.

[0]ATCMRMW

Enables 64-bit stores for the ATCM. When enabled, the processor uses read-modify-write to ensure that all reads and writes presented on the ATCM port are 64 bits wide.[e]

0 = Disabled

1 = Enabled.

The primary input RMWENRAMm[0] defines the reset value.

[a] This bit is RAZ if both caches have neither ECC nor parity.

[b] This bit is only supported if parity error generation is implemented in your design.

[c] This bit has no effect unless the Floating Point Unit (FPU) has been configured, see Configurable options.

[d] This bit has no effect unless TCM ECC logic has been configured for the respective TCM interface, see Configurable options.

[e] This feature is not available when the TCM interface has been built with 32-bit ECC.


To access the Secondary Auxiliary Control Register, read or write CP15 with:

MRC p15, 0, <Rd>, c15, c0, 0 ; Read Secondary Auxiliary Control Register
MCR p15, 0, <Rd>, c15, c0, 0 ; Write Secondary Auxiliary Control Register
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