Cortex-R5 and Cortex-R5F Technical Reference Manual: 4.3.16. c1, System Control Register

4.3.16. c1, System Control Register

The SCTLR characteristics are:

Purpose

Provides control and configuration information for:

memory alignment, endianness, protection, and fault behavior
MPU and cache enables and cache replacement strategy
interrupts and the behavior of interrupt latency
the location for exception vectors
program flow prediction.

Usage constraints

The SCTLR is:

a read/write register
accessible in Privileged mode only.
Attempts to read or write the SCTLR from User mode result in an Undefined Instruction exception.

Configurations

Available in all processor configurations.

Attributes

See Table 4.24.

Figure 4.27 shows the SCTLR bit assignments.

Figure 4.27. SCTLR bit assignments

Table 4.24 shows the SCTLR bit assignments.

Table 4.24. SCTLR bit assignments

Bits	Name	Function
[31]	IE	Identifies little or big instruction endianness in use: 0 = little-endianness 1 = big-endianness. The primary input CFGIE defines the value. This bit is read-only.
[30]	TE	Thumb exception enable: 0 = enable ARM exception generation 1 = enable Thumb exception generation. The primary input TEINIT defines the reset value.
[29]	AFE	Access Flag Enable. On the processor this bit is SBZ.
[28]	TRE	TEX Remap Enable. On the processor this bit is SBZ.
[27]	NMFI	NMFI, non-maskable fast interrupt enable: 0 = Software can disable FIQs 1 = Software cannot disable FIQs. This bit is read-only. The configuration input CFGNMFIm defines its value.
[26]	-	SBZ.
[25]	EE	Determines how the E bit in the CPSR is set on an exception: 0 = CPSR E bit is set to 0 on an exception 1 = CPSR E bit is set to 1 on an exception. The primary input CFGEE defines the reset value.
[24]	VE	Configures vectored interrupt: 0 = exception vector address for IRQ is `0x00000018` or `0xFFFF0018`. See V bit. 1 = VIC controller provides handler address for IRQ. The reset value of this bit is 0.
[23:22]	-	SBO.
[21]	FI	Fast Interrupts enable. On the processor Fast Interrupts are always enabled. This bit is SBO.
[20]	-	SBZ.
[19]	DZ	Divide by zero: 0 = do not generate an Undefined Instruction exception 1 = generate an Undefined Instruction exception. The reset value of this bit is 0.
[18]	-	SBO.
[17]	BR	MPU background region enable.
[16]	-	SBO.
[15]	-	SBZ.
[14]	RR	Round-robin bit, controls replacement strategy for instruction and data caches: 0 = random replacement strategy 1 = round-robin replacement strategy. The reset value of this bit is 0. The processor always uses a random replacement strategy, regardless of the state of this bit.
[13]	V	Determines the location of exception vectors: 0 = normal exception vectors selected, address range = `0x00000000`-`0x0000001C` 1 = high exception vectors (HIVECS) selected, address range = `0xFFFF0000-0xFFFF001C`. The primary input VINITHIm defines the reset value.
[12]	I	Enables L1 instruction cache: 0 = instruction caching disabled. This is the reset value. 1 = instruction caching enabled. If no instruction cache is implemented, then this bit is SBZ.
[11]	Z	Branch prediction enable bit. The processor supports branch prediction. This bit is SBO. The ACTLR can control branch prediction, see c1, Auxiliary Control Register.
[10]	SW	Enables `SWP` and `SWPB` instructions 0 = `SWP` and `SWPB` are Undefined 1 = `SWP` and `SWPB` are executed with full locking support on the bus The reset value of this bit is 0.^[a]
[9:7]	-	SBZ.
[6:3]	-	SBO.
[2]	C	Enables L1 data cache: 0 = data caching disabled. This is the reset value. 1 = data caching enabled. If no data cache is implemented, then this bit is SBZ.
[1]	A	Enables strict alignment of data to detect alignment faults in data accesses: 0 = strict alignment fault checking disabled. This is the reset value. 1 = strict alignment fault checking enabled.
[0]	M	Enables the MPU: 0 = MPU disabled. This is the reset value. 1 = MPU enabled. If no MPU is implemented, this bit is SBZ.
^[a]Unless explicitly enabled, `SWP` and `SWPB` are Undefined

To use the SCTLR, ARM recommends that you use a read-modify-write technique. To access the SCTLR, read or write CP15 with:

MRC p15, 0, <Rd>, c1, c0, 0 ; Read SCTLR

MCR p15, 0, <Rd>, c1, c0, 0 ; Write SCTLR

Attempts to read or write the SCTLR from User mode results in an Undefined Instruction exception.

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