6.3.8. c9, Event Type Selection Register

There are three Event Type Select Registers in the processor, PMXEVTYPER0 to PMXEVTYPER2, each corresponding to one of the Performance Monitor Count (PMXEVCNTR) Registers, PMXEVCNTR0 to PMXEVCNTR2. The register to be accessed is determined by the value in the PMSELR.

The PMXEVTYPER Register characteristics are:

Purpose

Selects the events you want a PMXEVCNTR Register to count.

Usage constraints

The PMXEVTYPER Register is:

  • A read/write register

  • Accessible in:

Configurations

Available in all processor configurations.

Attributes

Figure 6.7 shows the bit assignments.

Figure 6.7. PMXEVTYPERx Register bit assignments

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Table 6.8 shows the bit assignments.

Table 6.8. PMXEVTYPERx Register bit functions

Bits

Name Function
[31:8]-RAZ or SBZP.
[7:0]SEL

Event number selected, see Table 6.1 for values.

The reset value of this field is Unpredictable.


To access the PMXEVTYPERx Register, read or write CP15 with:

MRC p15, 0, <Rd>, c9, c13, 1 ; Read  PMXEVTYPERx Register
MCR p15, 0, <Rd>, c9, c13, 1 ; Write PMXEVTYPERx Register

The absolute counts of events recorded might vary because of pipeline effects. This has negligible effect except in cases where the counters are enabled for a very short time.

In addition to the counters within the processor, most of the events that Table 6.1 shows are available to the ETM unit or other external trace hardware to enable monitoring of the events. For information on how to monitor these events, see the CoreSight ETM-R5 Technical Reference Manual.

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