Cortex-R5 and Cortex-R5F Technical Reference ManualRevision: r1p1
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4.3.19. c1, Coprocessor Access Control Register

The CPACR characteristics are:

Purpose

Sets access rights for coprocessors.

Usage constraints

The CPACR is:

  • A read/write register.

  • Accessible in Privileged mode only.

  • Because this processor does not support coprocessors CP0 through CP9, CP12, and CP13, bits [27:24] and [19:0] in this register are read-as-zero and ignore writes.

  • CPACR has no effect on access to CP14, the debug control coprocessor, or CP15, the system control coprocessor. The only other coprocessor that the Cortex-R5F CPU includes is the FPU, CP10, and CP11. This register enables software to determine if the FPU exists in the CPU.

Configurations

Available in all processor configurations.

Attributes

See Table 4.27.

Figure 4.30 shows the CPACR bit assignments.

Figure 4.30. CPACR bit assignments

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Table 4.27 shows the CPACR bit assignments.

Table 4.27. CPACR bit assignments

Bits

Name Function
[31]ASEDIS

Advanced-SIMD disable. Read only.

0 = FPU is not configured

1 = FPU is configured, Advanced SIMD is not available.

[30]D32DIS

D16-D31 disable. Read only.

0 = FPU is not configured

1 = FPU is configured, VFP registers D16-D32 are not available.

[29:28]-Read as Zero.
[27:26]cp13Read as Zero.
[25:24]cp12
[23:22]cp11

Defines access permissions for the FPU.

If the FPU is not included for this processor, these bits are RAZ/WI.

If the FPU is included, both cp10 and cp11 must be programmed to the same value:

b00 = Access denied. Attempts to access generates an Undefined Instruction exception. This is the reset value.

b01 = Privileged mode access only

b10 = Reserved

b11 = Privileged and User mode access.

[21:22]cp10
[19:18]cp9Read as Zero.
[17:16]cp8
[15:14]cp7
[13:12]cp6
[11:10]cp5
[9:8]cp4
[7:6]cp3
[5:4]cp2
[3:2]cp1
[1:0]cp0

To access the CPACR, read or write CP15 with:

MRC p15, 0, <Rd>, c1, c0, 2 ; Read CPACR

MCR p15, 0, <Rd>, c1, c0, 2 ; Write CPACR
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