10.2.2. Standby mode

Standby mode allows most of the clocks of the device to be disabled, while keeping the design powered up. This reduces the power drawn to the static leakage current, plus a tiny clock power overhead required to enable the device to wake up from the Standby mode.

Entry into Standby mode is performed by executing the Wait For Interrupt (WFI) instruction or Wait For Event (WFE) instruction. To ensure that the entry into the Standby mode does not affect the memory system on a Cortex-R5 CPU, the WFI and WFE instructions automatically performs a Data Synchronization Barrier operation. This ensures that all explicit memory accesses occur before the WFI or WFE has completed. When this has happened, the CPU stops fetching instructions and asserts nWFIPIPESTOPPEDm or nWFEPIPESTOPPEDm as appropriate, to indicate that it is in Standby mode.

When the CPU is in Standby mode and it has no outstanding AXI-slave or debug-APB transactions or ACP invalidate requests, then it stops the clock to the majority of its logic. When the CPU clocks are stopped the nCLKSTOPPEDm signal is asserted. If the DBGNOCLKSTOP input is asserted, the CPU does not stop its clocks or assert nCLKSTOPPEDm when in Standby mode.

When the processor is in Standby mode and the AXI slave interface or debug-APB interface receives a transaction or an ACP invalidate request is generated, the processor clocks are temporarily restarted and nCLKSTOPPEDm is deasserted to enable it to service the transaction, but it does not return to Run mode.

The CPU exits Standby mode and returns to Run mode in response to a variety of events, depending on whether Standby mode was entered using WFI or WFE.

For WFI, the transition from Standby mode to Run mode is caused by:

For WFE, the transition from Standby mode to Run mode is caused by:

The debug request can be generated by an externally generated debug request, using the EDBGRQm pin on the processor, or from a Debug Halt instruction issued to the processor through the debug Advanced Peripheral Bus (APB).

Systems using the VIC interface must ensure that the VIC is not masking any interrupts that are required for restarting the processor when in standby mode.

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