7.1.1. Memory regions

Before the MPU is enabled, you must program at least one valid protection region. If you do not do this, the processor enters a state that only reset can recover.

When the MPU is disabled, no access permission checks are performed, and memory attributes are assigned according to the default memory map. See Table 7.1.

For more information on how to enable or disable the MPU, see MPU interaction with memory system.

Depending on the implementation, the MPU has a maximum of 12 or 16 regions. Using CP15 register c6 you can specify the following for each region:

Region base address

The base address defines the start of the memory region. You must align this to a region-sized boundary. For example, if a region size of 8KB is programmed for a given region, the base address must be a multiple of 8KB.


If the region is not aligned correctly, this results in Unpredictable behavior.

Region size

The region size is specified as a 5-bit value, encoding a range of values from 32 bytes, a cache-line length, to 4GB. Table 4.34 shows the encoding.


Each region can be split into eight equal sized non-overlapping subregions. An access to a memory address in a disabled subregion does not use the attributes and permissions defined for that region. Instead, it uses the attributes and permissions of a lower priority region or generates a background fault if no other regions overlap at that address. This enables increased protection and memory attribute granularity.

All region sizes between 256 bytes and 4GB support eight subregions. Region sizes below 256 bytes do not support subregions, and the subregion disable field is SBZ/UNP for regions of less than 256 bytes in size.

Region attributes

Each region has a number of attributes associated with it. These control how a memory access is performed when the processor accesses an address that falls within a given region. The attributes are:

  • Memory type, one of:

    • Strongly Ordered

    • Device

    • Normal

  • Shared or Non-shared

  • Non-cacheable

  • Write-through Cacheable

  • Write-back Cacheable

  • Read allocation

  • Write allocation.

See Memory types for more information about memory types, and Region attributes for a description of how to assign types and attributes to a region.

Region access permissions

Each region can be given no access, read-only access, or read/write access permissions for Privileged or all modes. In addition, each region can be marked as eXecute Never (XN) to prevent instructions being fetched from that region.

For example, if a User mode application attempts to access a Privileged mode access only region a permission fault occurs.

The ARM architecture uses constants known as inline literals to perform address calculations. The assembler and compiler automatically generate these constants and they are stored inline with the instruction code. To ensure correct operation, only a memory region that has permission for data read access can execute instructions. For more information, see the ARM Architecture Reference Manual. For information about how to program access permissions, see Table 4.38.

Instructions cannot be executed from regions with Device or Strongly-Ordered memory type attributes.

Copyright © 2010-2011 ARM. All rights reserved.ARM DDI 0460C