1.7.2. Design flow

The Cortex-R5 processor is delivered as synthesizable RTL. Before it can be used in a product, it must go through the following process:


The implementer configures and synthesizes the RTL to produce a hard macrocell. This might include integrating RAMs into the design.


The integrator connects the implemented design into a SoC. This includes connecting it to a memory system and peripherals.


This is the last process. The system programmer develops the software required to configure and initialize the Cortex-R5 processor, and tests the required application software.

Each process can be performed by a different party. Implementation and integration choices affect the behavior and features of the Cortex-R5 processor. The implementer can implement a macrocell that includes some of the SoC components in addition to the Cortex-R5 processor. In this situation, they must perform some of the integration before implementation. The integrator of such a macrocell has fewer integration tasks to perform, and fewer option choices to make.

The operation of the final device depends on:

Build configuration

The implementer chooses the options that affect how the RTL source files are pre-processed. These options usually include or exclude logic that affects one or more of the area, maximum frequency, and features of the resulting macrocell.

For example, the BTCM interface can be configured to have zero, one (B0TCM) or two (B0TCM and B1TCM) ports. If one port is chosen, the logic for the second port is excluded from the macrocell, although the pins remain, and the second port (B1TCM) cannot be used on that macrocell.

Configuration inputs

The integrator configures some features of the Cortex-R5 processor by tying inputs to specific values. These configurations affect the start-up behavior before any software configuration is made. They can also limit the options available to the software.

For example, if the build configuration for the macrocell includes both BTCM ports, the integrator can choose how many ports to actually use, and therefore how many RAMs must be integrated with the macrocell. If the integrator only wishes to use one BTCM port, they can connect RAM to the B0TCM port only, and tie the ENTCM1IFm input to zero to indicate that the B1TCM is not available.

Software configuration

The programmer configures the Cortex-R5 processor by programming particular values into registers. This affects the behavior of the Cortex-R5 processor.

For example, the enable bit in the BTCM Region Register controls whether or not memory accesses are performed to the BTCM interface. However, the BTCM cannot, and must not, be enabled if the build configuration does not include any BTCM ports, or if the pin configuration indicates that no RAMs have been integrated onto the BTCM ports.


This manual refers to implementation-defined features that are applicable to build configuration options. Reference to a feature that is included means that the appropriate build and pin configuration options are selected. Reference to an enabled feature means one that has also been configured by software.

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