8.3.1. Faults

The classes of fault that can occur are:

MPU faults

The MPU can generate an abort for various reasons. See MPU faults for more information. MPU faults are always synchronous, and take priority over other types of abort. If an MPU fault occurs on an access that is not in the TCM, and is to one of the peripheral ports, is Non-cacheable, or has generated a cache-miss, the AXI/AHB transactions for that access are not performed.

External faults

A memory access performed through the AXI master interface or the AXI peripheral port can generate two different types of error response, a slave error (SLVERR) or decode error (DECERR). These are known as external errors, because they are generated by the AXI system outside the processor. Synchronous aborts are generated for instruction fetches, data loads, exclusive stores, and data stores to strongly-ordered-type memory. Non-exclusive stores to normal-type or device-type memory generate asynchronous aborts.


  • An AXI slave that cannot handle exclusive transactions returns OKAY in response to an exclusive read. This is also treated as an external error, and the processor behaves as if the response was SLVERR.

  • Exclusive doubleword transactions to shared memory on the AXI peripheral port or exclusive transactions to shared memory on the AHB peripheral port are aborted. They are treated as synchronous external errors, and the processor behaves as if the response was SLVERR.

  • An AHB peripheral port slave response of ERROR is treated by the processor as a response of SLVERR.

Cache and TCM parity and ECC errors

If the processor has been configured with the appropriate build options, it can detect data errors occurring in the cache and TCM RAMs using parity or ECC logic. For more information on cache errors, see Handling cache parity errors and Handling cache ECC errors. For more information on TCM errors, see About the error detection and correction schemes. Depending on the software configuration of the processor, these errors are either ignored, generate an abort, are automatically corrected without generating an abort, or are corrected and generate an abort. If the processor is in debug-halt-state, an error that is otherwise automatically corrected generates an abort.

Parity and ECC errors can only occur on reads, although these reads might be a side-effect of store instructions. Aborts generated by loads are always synchronous. Aborts generated by store instructions to the TCM are also always synchronous, while those to the cache are always asynchronous. These errors can also occur on some cache-maintenance operations, see Errors on cache maintenance operations, and generate asynchronous aborts.

Many of the parity and ECC errors are also signaled by the generation of events. See Chapter 6 Events and Performance Monitor. Some of these events are generated when the error is detected, regardless of whether or not an abort is taken. Aborts are only taken when a memory access with an error is committed. Others are signaled when and only when the abort is taken.

Any parity or ECC error that can be corrected by the processor is considered to be a correctable fault, regardless of whether or not the processor is configured to correct the fault.

TCM external faults

The TCM port includes signals that can be used to signal an error on a TCM transaction. If enabled, this causes the processor to take the appropriate type of abort for instruction and data accesses, or to generate a SLVERR response to an AXI-slave transaction. Write transactions always generate asynchronous aborts, while read transactions always generate synchronous aborts.

An error signaled on a read transaction can also signal a retry request, that requests that the processor retry the same operation rather than take an exception.

A retry request from the TCM port is considered to be a recoverable error. All correctable ECC faults are also considered to be recoverable.

Debug events

The debug logic in the processor can be configured to generate breakpoints or vector capture events on instruction fetches, and watchpoints on data accesses. If the processor is software-configured for monitor-mode debugging, an abort is taken when one of these events occurs, or when a BKPT instruction is executed. For more information, see Chapter 12 Debug.

Synchronous and asynchronous aborts

See Aborts for more information about the differences between synchronous and asynchronous aborts.

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