8.8.3. Data-cache error events

The D-Cache can generate fatal and correctable errors, and therefore has four events, one for each type of error in the data RAM and in the tag or dirty RAMs. These events are only signaled for non-speculative data accesses, cache line evictions, coherency maintenance operations, and certain cache maintenance operations. See Cache error detection and correction.

Copyright © 2010-2011 ARM. All rights reserved.ARM DDI 0460C