9.7.8. AHB peripheral port transfers

The processor conforms to the AHB-Lite specification, but it does not generate all the AHB transaction types that the specification permits. This section describes the types of AHB transaction that the Cortex-R5 AHB peripheral port does not generate. If you are designing an AHB slave to work only with the Cortex-R5 processor AHB peripheral port, you can take advantage of these restrictions and the interface attributes described in previous sections to simplify the slave.

This section also contains tables that show some of the types of AHB burst that the processor generates. However, because a particular type of transaction is not shown here does not mean that the processor does not generate such a transaction.

Note

An AHB slave device connected to the Cortex-R5 AHB master port must be capable of handling every kind of transaction permitted by the AHB specification, except where there is an explicit statement in this chapter that such a transaction is not generated. You must not infer any additional restrictions from the example tables given.

Restrictions on AHB peripheral port transfers describes restrictions on the type of transfers that the Cortex-R5 AHB peripheral port generates.

The following sections give examples of transfers generated by the AHB peripheral port:

Restrictions on AHB peripheral port transfers

The Cortex-R5 AHB peripheral port applies the following restrictions to the AHB transactions it generates:

  • A burst never transfers more than eight bytes.

  • The burst length is never more than two transfers.

  • No transaction ever crosses a 8-byte boundary in memory

  • All bursts are either single or 1-beat incrementing bursts, that is, HBURSTPm[2:0] is either SINGLE or INCR.

  • The transfer type, that is, HTRANSPm[2:0] is never BUSY.

  • The transfer size is never greater than 32 bits because it is a 32-bit AHB bus.

  • If the transfer size is 8 bits or 16 bits then the burst length is always one transfer.

  • All transactions are data accesses, that is HPROTPm[0] is always 1.

  • Transactions to Device and Strongly Ordered memory are always to addresses that are aligned for the transfer size.

  • Locked accesses are always to addresses that are aligned for the transfer size.

Strongly Ordered and Device transactions

A load or store instruction, to or from Strongly Ordered or Device memory, always generates AHB transactions of the size implied by the instruction. All accesses using LDM, STM, LDRD or STRD instructions to Strongly Ordered or Device memory occur as 32-bit transfers.

LDRB

Table 9.59 shows the values of HADDRPm[1:0], HBURSTPm, and HSIZEPm for an LDRB from bytes 0-3 in Strongly Ordered or Device memory.

Table 9.59. LDRB transfers

Address[1:0]HADDRPm[1:0]HBURSTPm HSIZEPm
0x0 (byte 0)0x00Single8-bit
0x1 (byte 1)0x01Single8-bit
0x2 (byte 2)0x02Single8-bit
0x3 (byte 3)0x03Single8-bit

LDRH

Table 9.60 shows the values of HADDRPm[1:0], HBURSTPm, and HSIZEPm for an LDRH from halfwords 0-1 in Strongly Ordered or Device memory.

Table 9.60. LDRH transfers

Address[1:0]HADDRPm[1:0]HBURSTPm HSIZEPm
0x0 (halfword 0)0x00Single16-bit
0x2 (halfword 1)0x02Single16-bit

Note

A load of a halfword from Strongly Ordered or Device memory addresses 0x1 or 0x3 generates an alignment fault.

LDR or LDM of one register

Table 9.61 shows the values of HADDRPm[1:0], HBURSTPm, and HSIZEPm for an LDR or an LDM that transfers one register, an LDM1, in Strongly Ordered or Device memory.

Table 9.61. LDR or LDM of one register

Address[1:0]HADDRPm[1:0]HBURSTPm HSIZEPm
0x0 (word 0)0x00Single32-bit

Note

A load of a word from Strongly Ordered or Device memory addresses 0x1, 0x02, 0x3, 0x5, 0x06, or 0x7 generates an alignment fault.

LDM that transfers five registers

Table 9.62 shows the values of HADDRPm[1:0], HBURSTPm, and HSIZEPm for an LDM that transfers five registers, an LDM5, in Strongly Ordered or Device memory.

Table 9.62. LDM that transfers five registers

Address[1:0]HADDRPm[1:0]HBURSTPm HSIZEPm
0x0 (word 0)

0x00

0x04

Incr32-bit

0x08

0x0C

Incr32-bit
0x10Single32-bit
0x4 (word 1)0x04Single32-bit

0x08

0x0C

Incr32-bit

0x10

0x14

Incr32-bit

Note

A load of a word from Strongly Ordered or Device memory addresses 0x1, 0x2, or 0x3 generates an alignment fault.

STRB

Table 9.63 shows the values of HADDRPm[1:0], HBURSTPm, and HSIZEPm for an STRB from bytes 0-3 in Strongly Ordered or Device memory.

Table 9.63. STRB transfers

Address[1:0]HADDRPm[1:0]HBURSTPm HSIZEPm
0x0 (byte 0)0x00Single8-bit
0x1 (byte 1)0x01Single8-bit
0x2 (byte 2)0x02Single8-bit
0x3 (byte 3)0x03Single8-bit

STRH

Table 9.60 shows the values of HADDRPm[1:0], HBURSTPm, and HSIZEPm for an STRH from halfwords 0-1 in Strongly Ordered or Device memory.

Table 9.64. STRH transfers

Address[1:0]HADDRPm[1:0]HBURSTPm HSIZEPm
0x0 (halfword 0)0x00Single16-bit
0x2 (halfword 1)0x02Single16-bit

Note

A store of a halfword to Strongly Ordered or Device memory addresses 0x1 or 0x3 generates an alignment fault.

STR of one register

Table 9.65 shows the values of HADDRPm[1:0], HBURSTPm, and HSIZEPm for an STR that transfers one register, an STR1, in Strongly Ordered or Device memory.

Table 9.65. STR of one register

Address[1:0]HADDRPm[1:0]HBURSTPm HSIZEPm
0x0 (word 0)0x00Single32-bit

Note

A store of a word to Strongly Ordered or Device memory addresses 0x1, 0x2, or 0x3 generates an alignment fault.

STM of five registers

Table 9.66 shows the values of HADDRPm[1:0], HBURSTPm, and HSIZEPm for an STM that transfers five registers, an STM5, over the AHB master port to Strongly Ordered or Device memory.

Table 9.66. STM of five registers

Address[1:0]HADDRPm[1:0]HBURSTPm HSIZEPm
0x0 (word 0)

0x00

0x04

Incr32-bit

0x08

0x0C

Incr32-bit
0x10Single32-bit
0x4 (word 1)0x04Single32-bit

0x08

0x0C

Incr32-bit

0x10

0x14

Incr32-bit

Note

A store of a word from Strongly Ordered or Device memory addresses 0x1, 0x2, 0x3, 0x5, 0x6, or 0x7 generates an alignment fault.

Normal reads

Load instructions accessing Normal memory generate AHB peripheral port bursts that might not be the same size or length as the instruction implies. The tables in this section give examples of AHB transactions that might result from various load instructions, accessing various addresses in Normal memory. They are examples only, and are not an exhaustive description of the AHB transactions.

LDRH

Table 9.67 shows possible values of HADDRPm[1:0], HBURSTPm, and HSIZEPm for an LDRH from bytes 0 to 7 in Normal memory.

Table 9.67. LDRH transfers in Normal memory

Address[1:0]HADDRPm[1:0]HBURSTPm HSIZEPm
0x0 (byte 0)0x00Single16-bit
0x1 (byte 1)0x01Single8-bit
0x02Single8-bit
0x2 (byte 2)0x02Single16-bit
0x3 (byte 3)0x03Single8-bit
0x04Single8-bit
0x4 (byte 4)0x04Single16-bit
0x5 (byte 5)0x05Single8-bit
0x06Single8-bit
0x6 (byte 6)0x06Single16-bit
0x7 (byte 7)[a]0x07Single8-bit
0x08Single8-bit

[a] AHB peripheral port transactions do not cross a double word boundary.


LDR

Table 9.68 shows possible values of HADDRPm[1:0], HBURSTPm, and HSIZEPm for an LDR from Normal memory.

Table 9.68. LDR transfers in Normal memory

Address[1:0]HADDRPm[1:0]HBURSTPm HSIZEPm
0x0 (byte 0, word 0)0x00Single32-bit
0x1 (byte 1)0x01Single8-bit
0x02Single16-bit
0x04Single8-bit
0x2 (byte 2)0x02Single16-bit
0x04Single16-bit
0x3 (byte 3)0x03Single8-bit
0x04Single16-bit
0x06Single8-bit

Normal writes

Store instructions accessing Normal memory generate AHB peripheral port bursts that might not be the same size or length as the instruction implies. The tables in this section give examples of AHB transactions that might result from various store instructions, accessing various addresses in Normal memory. They are examples only, and are not an exhaustive description of the AHB transactions.

STRH

Table 9.69 shows possible values of HADDRPm[1:0], HBURSTPm, and HSIZEPm for an STRH from bytes 0 to 3 in Normal memory.

Table 9.69. STRH transfers in Normal memory

Address[1:0]HADDRPm[1:0]HBURSTPm HSIZEPm
0x0 (byte 0)0x00Single16-bit
0x1 (byte 1)0x01Single8-bit
0x02Single8-bit
0x2 (byte 2)0x02Single16-bit
0x3 (byte 3)0x03Single8-bit
0x04Single8-bit

STR or STM of one register

Table 9.70 shows possible values of HADDRPm[1:0], HBURSTPm, and HSIZEPm for an STR to Normal memory.

Table 9.70. STR transfers in Normal memory

Address[1:0]HADDRPm[1:0]HBURSTPm HSIZEPm
0x0 (byte 0, word 0)0x00Single32-bit
0x1 (byte 1)0x01Single8-bit
0x02Single16-bit
0x04Single8-bit
0x2 (byte 2)0x02Single16-bit
0x04Single16-bit
0x3 (byte 3)0x03Single8-bit
0x04Single16-bit
0x06Single8-bit

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