6.2. About the PMU

The PMU consists of three event counting registers, one cycle counting register and 12 CP15 registers, for controlling and interrogating the counters. The performance monitoring registers are always accessible in Privileged mode. You can use the User Enable (PMUSERENR) Register to make all of the performance monitoring registers, except for the Interrupt Enable Set (PMINTENSET), and Interrupt Enable Clear (PMINTENCLR) Registers, accessible in User mode.

All three event counters are read and written through the same CP15 register. The Performance Counter Selection (PMSELR) Register determines which counter is read or written. The three Event Selection registers, one per counter, are read and written through one CP15 register in the same way.

Using the control registers, you can enable or disable each of the event counters individually, and read and reset the overflow flag for each counter. Any or all of the counters can be enabled to assert an interrupt request output, nPMUIRQm, on overflow.

When the processor is in Debug halt state:

For more information on Debug halt state see Chapter 12 Debug.

The PMU only counts events when non-invasive debug is enabled, that is, when either DBGENm or NIDENm inputs are asserted. The Cycle Count (PMCCNTR) Register is always enabled regardless of whether non-invasive debug is enabled, unless the DP bit of the PMCR register is set. See c9, Performance Monitor Control Register.

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