10.2.7. Power mode interaction with debug

When one of the Cortex-R5 CPUs is in Standby mode and a debug-APB access to one of the core registers is received, the clocks for the CPU are restarted, if required, so that the transaction can be serviced as normal. When the transaction is complete, the clock is, gated off again if appropriate.

When a CPU is in Shutdown mode or Dormant mode, the core debug registers, for example. DBGDSCR, are unavailable and an error response is signalled for transactions to these registers. The debug-APB interface and the debug domain registers, for example DIDR, remain available as normal. The power-down status is indicated by the DBGPRSR. See Device Power-down and Reset Status Register.

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