10.2.6. Power mode interaction with ACP

When a CPU is in Standby mode, and a transaction that requires coherency is received by the ACP, the clock for the CPU is restarted, if required, so that coherency maintenance operations can be handled as normal. When the ACP is idle again the clock is gated off again, if appropriate,

When a CPU is in Dormant mode, then its cache contents are live, but it cannot respond to coherency maintenance operations that the ACP generates. For this CPU, for ACP transactions requiring coherency, the coherency maintenance operations information signals indicate that all addresses were not cached, that is, BMISSCS[m] is asserted, and indicate that at least one address was cached and potentially dirty, BHITDIRTYCS[m]. Because this is usually considered erroneous, ARM recommends that the system is built so that transactions requiring coherency cannot be received by the processor, when one or both of the CPUs are in Dormant mode.

When a CPU is in Shutdown mode, its cache contents are lost and therefore there are no coherency issues with that cache. For this CPU, the coherency maintenance operations information signals indicate that all addresses were not cached, that is, BMISSCS[m] is asserted, and do not indicate that at least one address was cached and potentially dirty, that is, BHITDIRTYCS[m] is not asserted.

See Accelerator Coherency Port interface for more information about the ACP.

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