3.4. Coherency

In a system with multiple bus masters, memory coherency problems can occur when the masters access the same memory locations, if one or more of the masters has an associated cache. For example if there are two masters, A and B, each with its own level-one cache, the following problems can occur:

In a twin-CPU configuration of the Cortex-R5 processor, each CPU can have its own level-1 cache. The Cortex-R5 processor might also be integrated into a system with other bus masters. In both cases the coherency problems can occur.

There are a number of solutions to these problems, including:

Data is not shared

If the two masters never access the same data, there can be no coherency issues.

Data that is to be shared between masters is not cached

In the Cortex-R5 processor, data that is in a shared region is never cached in the level-1 caches, even if the region is also cacheable. However, if a Cortex-R5 CPU is connected to a level-2 cache, then data in a shared region might be cached in its level-2 cache, leading to coherency problems, depending on how the level-2 cache is configured. See Region attributes for information about setting memory region attributes.

Data that is to be shared between masters is only cached in coherent caches

If all the bus masters use the same level-2 cache, and do not cache the data in their level-1 cache, then the data stored in the level-2 cache is coherent.

Software coherency

Cache maintenance operations can be used to manipulate the caches so that shared data is visible to other bus masters. In the first example, after master A writes into its cache data that is to be shared by master B, it must also clean the appropriate cache locations to ensure that the level-2 memory has been updated. In the second example, after master A writes data to the level-2 memory, it must cause master B to invalidate the appropriate cache locations in its cache so that master B reads the new value from level-2 memory.

The requirement for cache-clean operations can be avoided by using write-through caching, but invalidate operations are always required. In all cases, barrier operations are required to ensure that the level-2 memory updates have taken place before the cache maintenance operations are performed. Cortex-R5 cache maintenance operations are described in Cache operations.

Hardware coherency

Coherency logic, associated with the masters and their caches, performs the appropriate cache manipulation operations to ensure coherency of data that is shared between the masters. ARM multi-processing (MP) technology provides hardware coherency between multiple CPUs and their associated caches within a cluster, for data that is in a shared memory region. A twin-CPU Cortex-R5 group is not an MP-cluster. No hardware coherency is provided between the two CPUs, see CPU configurations for more information. The Cortex-R5 processor does provide hardware coherency with an external master in limited situations using the ACP. See Accelerator Coherency Port interface for more information.

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