1.6. Test features

The processor is delivered as fully-synthesizable RTL and is a fully-static design. Scan-chains and test wrappers for production test can be inserted into the design by the synthesis tools during implementation. See the relevant reference methodology documentation for more information.

If the AXI-slave interface is included, production test of the processor cache and TCM RAMs can be done through the dedicated, pipelined MBIST interface. This interface shares some of the multiplexing present in the processor design.

In addition, you can use the AXI slave interface to read and write the cache RAMs and TCM. You can use this feature to test the cache RAMs in a running system. This might be required in a safety-critical system. The TCM can be read and written directly by the program running on the processor. You can also use the AXI slave interface for swapping a test program in to the TCMs for the processor to execute. See Accessing RAMs using the AXI slave interface for more information about how to access the RAMs using the AXI slave interface.

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