11.5.3. Exceptions

The FPU implements the VFPv3 architecture and sets the cumulative exception status flag in the FPSCR register as required for each instruction. The FPU does not support user-mode traps. The exception enable bits in the FPSCR read-as-zero, and cannot be written. The processor also has six output pins, FPIXCm, FPUFCm, FPOFCm, FPDZCm, FPIDCm, and FPIOCm, that each reflect the status of one of the cumulative exception flags. See FPU signals for a description of these outputs. You can mask each of these outputs masked by setting the corresponding bit in the Secondary Auxiliary Control Register.

See c1, Auxiliary Control Register for more information.

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