2.1. About the functions

Figure 2.1 shows the structure of the processor. Figure 2.2 shows the structure of a CPU within the processor

Figure 2.1. Processor block diagram

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Figure 2.2. CPU block diagram

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The PreFetch Unit (PFU) fetches instructions from the memory system, predicts branches, and passes instructions to the Data Processing Unit (DPU). The DPU executes all instructions and uses the Load/Store Unit (LSU) for data memory transfers. The PFU and LSU interface to the L1 memory system that contains L1 instruction and data caches and the TCM interfaces. The L1 caches in turn connect to the L2 memory system, and the LSU has a more direct connection to the L2 memory system by means of the peripheral port. The L1 data cache interfaces to the µSCU to perform cache maintenance as required for coherency with ACP transactions.

This section describes the main components of the processor:

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