9.4.1. AXI slave interface for cache RAMs

Note

You must not use the AXI slave to access the cache RAMs at the same time as the ACP. Ensure the ACP is idle before initiating AXI slave transactions to the cache RAMs.

You can use the AXI slave for software testing of the cache RAMs in functional mode. When the AXI slave is enabled to access the RAMs, the processor considers the caches as cache-off, so that the instruction and data requests cannot interact with AXI slave requests. In this state, only AXI slave requests can access the cache RAM and instruction and data requests from the processor are considered as non-cacheable and do not perform any lookup in the caches.

The AXI slave interface accesses each cache RAM individually.

On the instruction cache side the AXI slave can access:

On the data cache side, the AXI slave can access:

A simple decode of four address bits and four way address bits determines which of the data, tag, or dirty RAMs is accessed within the caches. The AXI access is given a SLVERR error response when access to nonexistent cache RAM is indicated.

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