9.6.2. Cache RAM access

This section contains the following:

Memory map when accessing the cache RAMs

The memory map is divided into 2 regions:

  • RAM-Access region

  • TRANSFER and AUX register access region

.

The TRANSFER register enables an AXI master to construct a single RAM access from multiple sub-word accesses, that might be required if the master data width is less than the RAM data width.

The AUX register provides access to Data RAM ECC and parity data, if implemented.

The RAM-Access region initiates all AXI-slave RAM accesses. Reads from this region return data and update the TRANSFER and AUX registers. Writes to this region combine with the data in the TRANSFER and AUX registers, before being committed to the RAM.

Table 9.28 describes the RAM-Access memory map and Table 9.29 describes the TRANSFER and AUX memory map.

Any address that is not listed in Table 9.28 or addresses that are explicitly listed as illegal returns a SLVERR.

Any fields marked as RAZ/WI refer to the RAMs. The TRANSFER and AUX registers are not guaranteed to be RAZ/WI.

Table 9.28. RAM-Access space

AxADDRSm bitsDescription
[22:19]

Block select:

0000 = single bank data RAM

0001 = tag RAM

0010 = dirty RAM[a]

0100 = double bank data RAM[a]

1000 = strobed double bank data RAM[a].

[18:15]

Bank select.

For D-Cache data RAMs:

  • Single bank mode. Accesses a single RAM-word:

    0001 = Bank 0 or 1

    0010 = Bank 2 or 3

    0100 = Bank 4 or 5

    1000 = Bank 6 or 7

    Bit [13] of the address determines which of the two banks is selected for each of these values.

    0 = lower numbered bank

    1 = higher numbered bank

  • Double bank mode. Accesses 2 RAM-words from contiguous banks:

    0001 = Bank 0 and 1

    0010 = Bank 2 and 3

    0100 = Bank 4 and 5

    1000 = Bank 6 and 7

  • Strobed double bank mode. Accesses 2 contiguous banks with byte-strobe support:

    0001 = Bank 0 and 1

    0010 = Bank 2 and 3

    0100 = Bank 4 and 5

    1000 = Bank 6 and 7

    Strobes used to access the selected banks are derived directly from the WSTRB signals for the access to the RAM-Access space.

For I_Cache data RAMs:

0001 = Bank 0

0010 = Bank 1

0100 = Bank 2

1000 = Bank 3

For tag[b][c] and dirty[a][d] RAMs:[15] = Bank 0[16] = Bank 1[17] = Bank 2[18] = Bank 3.

For tag-RAM reads, only one-hot encodings are supported.

For tag-RAM writes, all combinations are supported, the same data is written to all banks.

For dirty RAM accesses, all combinations are supported.

[14]

Indicates address space accessed:

0 = RAM-Access

[13:2]

For D_Cache double-bank data RAM accesses:

[13:3] = RAM index

[2] = bank select

For D_Cache single-bank RAM accesses:

[13] = bank select

[12:2] = RAM index

For I_Cache data RAM accesses:

[13:3] = RAM index

[2] = word select

For all other accesses:[13:12] = 0x0[11:3] = RAM index

[2] = word select

[1:0]Byte select

[a] D_Cache only.

[b] For tag-RAM reads, only one-hot encodings are supported.

[c] For tag-RAM writes, all combinations are supported. The same data is written to all banks.

[d] For dirty RAM accesses, all combinations are supported.


Table 9.29. TRANSFER/AUX space

AxADDRSm bitsDescription
[22:15]

0x0

[14]

Indicates address space accessed:

1 = TRANSFER/AUX

[13:4]0x0
[3]

Register accessed:

0 = TRANSFER

1 = AUX

[2]Word select
[1:0]Byte select

Only accesses to the RAM-Access space actually perform RAM accesses.

TRANSFER and AUX are intermediate registers that are used by the AXI slave logic to perform RAM accesses.

Note

The physical integration of the RAMs limits the granularity of RAM accesses. This means that:

  • A data chunk and its ECC or parity, if implemented, are always updated together.

  • It is not possible to access part of a RAM-word unless the RAM-integration guidelines for the processor require that the RAM itself must support this feature.

    This requirement exists only for the D_Cache data RAMs and dirty RAMs, that must be implemented by byte-writable RAMs. The AXI slave bus supports the full range of byte-write support to this RAM only.

Writes to the RAM-Access space update TRANSFER with the write data, then use this register, and possibly AUX, to write to the selected RAM.Reads from the RAM-Access space read the RAM contents into TRANSFER, and possibly AUX, and provide the requested portion of the read data from TRANSFER on the AXI interface.

To perform accesses outside these restrictions, you must perform a read-modify-write sequence.

You can also access the TRANSFER and AUX registers directly using the TRANSFER/AUX space. Such accesses do not actually perform RAM accesses. In this way RAM accesses are decoupled from AXI transactions, and a single RAM access can be decomposed into, or composed from, multiple AXI bus accesses. This enables, for example, a master capable only of sub-word accesses to get full access to the RAMs.

All accesses to the TRANSFER and AUX registers are cumulative. This means that data written to the TRANSFER and AUX registers, through direct AXI slave accesses, persists until it is overwritten. Reads from the cache RAMs, occurring as a side effect of AXI slave accesses to the RAM-Access space, also update these registers and overwrite any value previously written. This enables easier read-modify-write (RMW) operation by the master.

The TRANSFER register enables you to transfer data and ECC to the tag and dirty RAMs, and to transfer data to the data RAMs.

The AUX register is used only for transferring ECC to the data RAMs. If neither cache implements parity or ECC, direct accesses to the AUX register return a SLVERR.

For writes, you must ensure that all the data to be written to the selected RAM is initialized, either by prior accesses to TRANSFER/AUX, by the current access to RAM-Access or by a combination of both.

You can perform writes by a variety of sequences involving the RAM-Access space, and possibly also the TRANSFER/AUX space. For example, a write to a data RAM can be done by:

  • Multiple writes to the TRANSFER register and AUX register, followed by a single write, with potentially zeroed byte strobes, at the appropriate address to the RAM-Access space

  • A single write to the AUX register, if ECC is present, followed by a single write at the appropriate address to the RAM-Access space.

You can perform reads by a similarly varied number of sequences. For example, a read of a data RAM can be done by:

  • A single 64-bit read of the RAM-Access space followed by a single 64-bit read of the AUX register

  • A byte read of the RAM-Access space followed by several byte-reads to read the rest of the RAM data from the TRANSFER and AUX registers.

The format of the data, for reads and writes, depends on the RAM accessed and the error configuration of the RAM. These formats are described in the following tables. All writes must ensure that the write data is on the correct lane. Reads return data on the lanes described.

D_Cache data RAM single bank accesses

This section applies when you are performing a single bank access.

The location from which data bits are read, or to which they are written, depends on bit [0] of the RAM index. ECC or parity bits are written to, or read from, the lower byte of the AUX register.

Table 9.36 describes the format of the AUX register for D_Cache data RAM accesses, when ECC is configured.

Table 9.30. Data RAM AUX format, D_Cache, with ECC

BitDescription
[63:7]RAZ/WI
[6:0]ECC32[6:0]

Table 9.37 describes the format of the AUX register for data RAM, D_Cache, when parity is configured.

Table 9.31. Data RAM AUX format, D_Cache, with parity

BitDescription
[63:4]RAZ/WI
[3] parity for byte 3, data[31:24]
[2]parity for byte 2, data[23:16]
[1] parity for byte 1, data[15:8]
[0]parity for byte 0, data[7:0]

Table 9.38 describes the format of the AUX register for data RAM, D_Cache, when no error correction is configured.

Table 9.32. Data RAM AUX format, D_Cache, with no error correction

BitDescription
[63:0]RAZ/WI

RAM index[0] = 0
Writing

The data bits used are the result of the lower word of TRANSFER multiplexed with the lower word of the data sent to the RAM-Access space. The values of WSTRB used for this AXI transaction determine which is multiplexed in:

WSTRB=0

data is taken from TRANSFER

WSTRB=1

data is taken from the data bus

Reading

The data bits are written to the lower word of TRANSFER, and appear on the lower word of the AXI data bus.

The upper word of TRANSFER is set to zero.

RAM index[0] = 1
Writing

The data bits used are the result of the upper word of TRANSFER multiplexed with the upper word of the data sent to the RAM-Access space. The values of WSTRB used for this AXI transaction determine which is multiplexed in.

Reading

The data bits are written to the upper word of TRANSFER, and appear on the upper word of the AXI data bus.

I_Cache Data RAM access

Table 9.33 describes the format of the AUX register for data RAM, I-cache, when ECC is configured.

Table 9.33. Data RAM AUX format, I-cache, with ECC

BitDescription
[63:8]RAZ/WI
[7:0]ECC64[7:0] for double word, data[63:0]

Table 9.34 describes the format of the AUX register for data RAM, I-cache, when parity is configured.

Table 9.34. Data RAM AUX format, I-cache, with parity

BitDescription
[63:8]RAZ/WI
[7:0]Parity[7:0] for double word, data[63:0]

Table 9.35 describes the format of the AUX register for data RAM, I-cache, when no error correction is configured.

Table 9.35. Data RAM AUX format, I-cache, with ECC

BitDescription
[63:0]RAZ/WI

D_Cache data RAM double bank accesses

This section applies when you are performing a normal, or strobed, double bank access.

Normal accesses read or write all bytes of the doubleword being transferred. Strobed accesse read or write only those bytes specified by the corresponding bit in WSTRB. See Table 9.7

Table 9.36 describes the format of the AUX register for D_Cache data RAM accesses, when ECC is configured.

Table 9.36. Data RAM AUX format, D_Cache, with ECC

BitDescription
[63:15]RAZ/WI
[14:8]ECC32[6:0] for upper word, data[63:32]
[7]RAZ/WI
[6:0]ECC32[6:0] for lower word, data[31:0]

Table 9.37 describes the format of the AUX register for data RAM, D_Cache, when parity is configured.

Table 9.37. Data RAM AUX format, D_Cache, with parity

BitDescription
[63:12]RAZ/WI
[11]parity for byte 3 of upper word, data[63:56]
[10]parity for byte 2 of upper word, data[55:48]
[9]parity for byte 1 of upper word, data[47:40]
[8]parity for byte 0 of upper word, data[39:32]
[7:4]RAZ/WI
[3] parity for byte 3 of lower word, data[31:24]
[2]parity for byte 2 of lower word, data[23:16]
[1] parity for byte 1 of lower word, data[15:8]
[0]parity for byte 0 of lower word, data[7:0]

Table 9.38 describes the format of the AUX register for data RAM, D_Cache, when no error correction is configured.

Table 9.38. Data RAM AUX format, D_Cache, with ECC

BitDescription
[63:0]RAZ/WI

Tag RAM access

Table 9.39 describes the format of the TRANSFER register for tag RAM, when using ECC.

Table 9.39. Tag RAM TRANSFER ECC format

BitDescription
[63:30]RAZ/WI
[29:23]

ECC32 - selected way

[22]Valid - selected way
[21:0]Tag - selected way

Table 9.40 describes the format of the TRANSFER register for tag RAM, when using parity.

Table 9.40. Tag RAM TRANSFER parity format

BitDescription
[63:24]RAZ/WI
[23]Parity - selected way
[22]Valid - selected way
[21:0]Tag - selected way

Table 9.41 describes the format of the TRANSFER register for tag RAM, when no error correction is configured.

Table 9.41. Tag RAM TRANSFER format, without error correction

BitDescription
[63:23]RAZ/WI
[22]Valid - selected way
[21:0]Tag - selected way

Dirty RAM access

Table 9.42 describes the format of the TRANSFER register for dirty RAM, when ECC is configured.

Table 9.42. Dirty RAM TRANSFER format, with ECC

BitDescription
[63:31]RAZ/WI
[30:27]ECC32 - way 3
[26:25]Outer attributes - way 3
[24]Dirty - way 3
[23]RAZ/WI
[22:19]ECC32 - way 2
[18:17]Outer attributes - way 2
[16]Dirty - way 2
[15]RAZ/WI
[14:11]ECC32 - way 1
[10:9]Outer attributes - way 1
[8]Dirty - way 1Dirty - way 1
[7]RAZ/WI
[6:3]ECC32 - way 0
[2:1]Outer attributes - way 0
[0]Dirty - way 0

Table 9.43 describes the format of the TRANSFER register for dirty RAM, when parity, or no error correction, is configured.

Table 9.43. Dirty RAM TRANSFER format, without ECC

BitDescription
[63:27]RAZ/WI
[26:25]Outer attributes - way 3
[24]Dirty - way 3
[23:19]RAZ/WI
[18:17]Outer attributes - way 2
[16]Dirty - way 2
[15:11]RAZ/WI
[10:9]Outer attributes - way 1
[8]Dirty - way 1Dirty - way 1
[7:3]RAZ/WI
[2:1]Outer attributes - way 0
[0]Dirty - way 0

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