9.8. Accelerator Coherency Port interface

The optional Accelerator Coherency Port (ACP) provides memory coherency as introduced in Coherency between each CPU in the Cortex-R5 group and an external master.

The ACP has an AXI slave interface and an AXI master interface:

Each port is 64 bits wide, and conforms to the AMBA 3 AXI standard as described in the AMBA AXI Protocol Specification.

Within the AXI standard, the ACP slave port uses a number of extension signals to:

Within the AXI standard, the ACP master port uses a number of extension signals to:

See Bus ECC for more information on parity checking and generation in the ACP.

The ACP ports can run at the same frequency as the processor or at a lower synchronous frequency. See Clocking for more information.

The Cortex-R5 ACP memory coherency scheme only provides coherency between an external master connected to the ACP slave port and a CPU with a data cache in the Cortex-R5 group for memory regions configured as inner cacheable write-through in the CPU’s MPU. It does not provide coherency for memory regions configured as cacheable write-back.

Note

In a twin-CPU configuration, the ACP maintains memory coherency between the external master and each CPU with a data cache in the Cortex-R5 group, but not between the external master and a CPU without a data cache, or between the two CPUs.

For AXI write transactions going through the ACP and marked as coherent, AW channel sideband signal AWCOHERENTCS high, the ACP ensures that there is no cached copy of the data at these addresses in the CPU’s data cache when the AXI write completes.

When an AXI write from the external master appears on the ACP slave port’s AW channel, the ACP records some information about it and forwards the write transaction to the memory system on the ACP master port’s AW channel.

When the memory system sends the write response on the ACP master port’s B channel, the ACP records the response and recalls if the transaction was coherent.

If the transaction is not coherent, the ACP forwards the response to the external master on the ACP slave port’s B channel.

If the transaction is coherent, the ACP first sends coherency maintenance operations to the CPU’s data cache controller for the addresses spanned by the write transaction, and waits until the cache controller has acknowledged that all necessary coherency maintenance operations have been carried out to forward the write response to the ACP slave port’s B channel, along with information about the maintenance operations.

Coherency maintenance operations invalidate cache lines when a CPU’s data cache holds a copy of data at an address spanned by a coherent external write transaction. However if this cache line is dirty, it is not invalidated and the ACP indicates along with the write response that coherency was not maintained for this transaction.

For each CPU, information on the coherency maintenance operations includes:

If a transaction is not coherent, the ACP always indicates that all addresses were not cached and never indicates that at least one address was cached and potentially dirty.

If a CPU’s data cache controller cannot process coherency maintenance requests, because, for example, it is powered down, the ACP always indicates that all addresses were not cached and indicates that at least one address was cached and potentially dirty, only if coherency was not maintained for the write transaction.

Note

  • The ACP does not reorder transactions:

    • write address transactions appear on the ACP master port AW channel in the same order as they appeared on the ACP slave port AW channel

    • responses appear on the ACP slave port B channel in the same order as they appeared on the ACP master port B channel.

  • The ACP master port requires that the slave it connects to does not return a write response until it has received both the write data and the write address.

  • You must not use the ACP at the same time as the AXI slave is accessing the cache RAMs. If you use the AXI slave to access the cache RAMs, ensure that it is idle before initiating ACP transactions.

The ACP slave interface attributes are described in Table 9.71.

Table 9.71. ACP slave interface attributes

AttributeValue
Write acceptance capability4
Write interleave depth1

The ACP master interface attributes are described in Table 9.72.

Table 9.72. ACP master interface attributes

AttributeValue
Write issuing capability2
Write ID capability4
Write ID width2

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