9.1.1. Bus ECC

You can configure a Cortex-R5 processor with bus ECC to protect the integrity of AMBA bus signals. The bus ECC feature of the Low Latency Peripheral Port is configured separately from the other bus interfaces.

Bus ECC uses both parity and Single Error Correct Double Error Detect (SEC-DED) Error Correcting Codes (ECC). The Cortex-R5 processor computes and checks parity bits as odd or even, depending on the value of the PARITYLEVEL primary input, except for AXI handshake signals that have fixed, odd parity.

ECC and parity errors, detected by the Cortex-R5 processor, do not directly cause aborts, exceptions or otherwise affect the CPU operation. Instead, event primary outputs notify the system of correctable or fatal errors. The CPU treats all bus control and response signals as correct, even if parity errors are reported. It is possible that fatal, that is double-bit, ECC errors might cause more data corruption. This can result in the CPU operating on corrupted data, or behaving unpredictably, based on corrupted control or response signals.

Bus ECC functionality checks for errors on every bus transfer the CPU performs. This can include speculative accesses for which data is later discarded. The CPU:

AXI Interfaces

The Cortex-R5 processor uses the following scheme to protect AXI signals:

  • Fixed, odd parity on channel VALID and READY signals.

  • Parity on address and control payload signals. Each parity bit protects a maximum of eight payload bits.

  • SEC-DED ECC to protect read and write data payload.

AHB Interfaces

The Cortex-R5 processor uses the following scheme to protect AHB signals:

  • Parity on address and control signals. Each parity bit protects a maximum of eight payload bits

  • SEC-DED ECC to protect data payload.

Debug APB Interface

Bus ECC is not available for this interface.

Notifications

The Cortex-R5 bus ECC feature provides the following notifications:

  • Correctable errors on read data received by the AXI Master and Peripheral Port, through primary outputs.

  • Correctable errors on write data received by the AXI Slave through a primary output.

  • Logical address of transfers with correctable errors on master ports, to doubleword granularity.

  • Memory chip select and logical address of transfers with correctable errors on the AXI Slave, to doubleword granularity.

  • Fatal errors on AXI ports using one primary output bit per channel per port.

  • Fatal errors on the AHB Peripheral Port through a primary output.

  • A correctable bus fault event in the event bus, EVNTBUSm. See About the events.

  • A fatal bus fault event in the event bus, EVNTBUSm. See About the events.

  • Increments to correctable and fatal bus fault event counters for the Performance Monitoring Unit (PMU). See About the events.

Concurrent Bus Fault Events

The Cortex-R5 event bus and PMU logic monitors bus fault events on all Cortex-R5 AXI and AHB interfaces simultaneously. It merges bus faults that occur in the same CPU clock cycle, on different bus interfaces. For example, if correctable errors occur on both the AXI master and AXI slave, in the same CPU clock cycle, only one event is logged.

Bus Master Correctable Error Address Reporting

The Cortex-R5 processor has one primary output for reporting the logical address of a transfer with a correctable error, on the AXI master port, or the AXI and AHB Peripheral Ports. Concurrent correctable bus faults on the AXI master and the Peripheral Port cause the address to be reported for the AXI master only. Correctable errors do not occur concurrently on the AHB and AXI Peripheral Ports, see Peripheral interfaces for more information about the Cortex-R5 Peripheral Port.

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