9.7.9. Semaphores

The peripheral interfaces use the internal exclusive monitor of the processor L1 memory system to manage load, store and clear exclusive instructions to non-shared memory. The internal monitor checks exclusive accesses to shared memory and also, if necessary, any external monitor using the L2 memory interface. You can use these instructions to construct semaphores and ensure synchronization between different processes or processors. See the ARM Architecture Reference Manual for more information about how these instructions work.

Only exclusive instructions to shared memory result in exclusive accesses on the bus. Exclusive accesses to non-shared memory are marked as non-exclusive accesses on the bus.

Exclusive doubles to shared memory on LLPP Normal AXI or LLPP Virtual AXI (LDREXD and STREXD) are aborted. The AHB peripheral port cannot perform any exclusive accesses, so all exclusive accesses to shared memory on the AHB peripheral interface are aborted. The source of an abort because of a shared exclusive double to LLPP Normal AXI or LLPP Virtual AXI, or a shared exclusive to the AHB peripheral interface is encoded in the Data Fault Status Register (DFSR) as a Synchronous External AXI Slave Error.

The SWP and SWPB instructions can also be used for memory synchronization. Only swap instructions to shared memory are marked as locked accesses on the bus.

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