Appendix E. Revisions

This appendix describes the technical changes between released issues of this book.

Table E.1. Issue A

ChangeLocationAffects

First release

--

Table E.2. Differences between issue A and issue B

ChangeLocationAffects
Add ID values for r1p0Table 1-3 on page 1-16r1p0
Updated AMBA interface clock gatingClock gatingr1p0
System control register enables SWP and SWPB to be UndefinedTable 4.24r1p0
Single-precision only option for Cortex-R5F

Features

Table 1.1

Figure 4.45

Table 4.58

About the FPU programmers model

Media and VFP Feature Registers, MVFR0 and MVFR1

r1p0
Accessibility of Slave Port Control Register???All revisions
Additional description for c15, Build Options 1 Registerc15, Build Options 1 RegisterAll revisions
Update AXI slave address decode informationAXI slave interface for cache RAMsAll revisions
Update AXI slave characteristicsAXI slave characteristicsAll revisions
Changed RAM access using AXI slave interfaceAccessing RAMs using the AXI slave interfacer1p0
Register name corrections

STRH

DTR access mode

All revisions
MVFR1.LS change of usageTable 11.8r1p0

Table E.3. Differences between issue B and issue C

ChangeLocationAffects
Update revision informationTable 1-3 on page 1-16r1p1
Table 4.7
Table 4.15
Table 4.17
AXI master interface transfers
Correct RVPTYSm signal nameTable A.8All revisions
Add BVPTYCS signal descriptionTable A.10All revisions
Add ARCTLPTYS[3:0] signal descriptionTable A.8All revisions
Update RAM-Access space referenceCache RAM accessAll revisions
Update validation register short namesValidation RegistersAll revisions
Update descriptions of product revisionsTable 4.3All revisions
Table 12.6
Table 12.31
Table 11.4
Update register descriptionsThroughout manualAll revisions

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