2.4.1. Initialization

When the processor has started executing, but before you can run application software on the processor, it must be initialized, including loading the appropriate software-configuration. This section describes the steps that the software must take to initialize the processor after reset.

Most of the architectural registers in the processor, such as r0-r14, and s0-s31 and d0-d15 when floating-point is included, are not reset. Because of this, you must initialize these for all modes before they are used, using an immediate-MOV instruction, or a PC-relative load instruction. The Current Program Status Register (CPSR) is given a known value on reset. This is described in the ARM Architecture Reference Manual. The reset values for the CP15 registers are described along with the registers in Chapter 4 System Control .

In addition, before you run the application, you might want to:

Other initialization requirements are described in:

MPU

If the processor has been built with an MPU, before you can use it you must:

  • program and enable at least one of the regions

  • enable the MPU in the SCTLR.

See c6, MPU memory region programming registers. Do not enable the MPU unless at least one MPU region is programmed and active. If the MPU is enabled, before using the TCM interfaces you must program MPU regions to cover the TCM regions to give access permissions to them.

FPU

If the processor has been built with a Floating Point Unit (FPU) you must enable it before VFP instructions can be executed:

Note

Floating-point logic is only available with the Cortex-R5F processor.

Caches

If the processor has been built with instruction or data caches, these must be invalidated before they are enabled, otherwise Unpredictable behavior can occur. See Cache operations.

If you are using an error checking scheme in the cache, you must enable this by programming the Auxiliary Control Register before invalidating the cache, to ensure that the correct error code or parity bits are calculated when the cache is invalidated. See c1, Auxiliary Control Register. An invalidate all operation never reports any ECC or parity errors.

If you are using the ACP, you must perform the data cache invalidation before initiating coherent ACP transactions. Until then, you must not depend on the coherency maintenance information signals.

TCM

The processor does not initialize the TCM RAMs. It is not essential to initialize all the memory attached to the TCM interface but ARM recommends that you do. In addition, the main application might require you to preload instructions or data into the TCM. This section describes various ways that you can perform data preloading. You can also configure the processor to use the TCMs from reset.

Preloading TCMs

You can write data to the TCMs using either store instructions or the AXI slave interface. Depending on the method you choose, you might require:

  • particular hardware on the SoC that you are using

  • boot code

  • a debugger connected to the processor.

Methods to preload TCMs include:

Memory copy with running boot code

The boot code includes a memory copy routine that reads data from a ROM, and writes it into the appropriate TCM. You must enable the TCM to do this, and it might be necessary to give the TCM one base address while the copy is occurring, and a different base address when the application is being run.

Copy data from the debug communications channel

The boot code includes a routine to read data from the Debug Communications Channel (DCC) and write it into the TCM. The debug host feeds the data for this operation into the DCC by writing to the appropriate registers on the processor APB debug port.

Execute code in debug halt state

The processor is put into debug halt state by the debug host, that then feeds instructions into the processor through the Instruction Transfer Register (DBGITR). The processor executes these instructions, that replace the boot code in either of the previous two methods.

DMA into TCM

The SoC includes a Direct Memory Access (DMA) device that reads data from a ROM, and writes it to the TCMs through the AXI slave interface.

Write to TCM directly from debugger

A Debug Access Port (DAP) in the system is used to generate AMBA transactions to write data into the TCMs through the AXI slave interface. This DAP is controlled from the debug host through a JTAG chain.

Preloading TCMs with ECC

The error codes in the TCM RAM, if configured with an error scheme, are not initialized by the processor. Before a RAM location is read with ECC checking enabled, the error codes must be initialized. To calculate the error code correctly, the logic must have all the data in the data chunk that those bits protect. Therefore, when the TCM is being initialized, the writes must be of the same width and aligned to the data chunk that the error scheme protects.

You can initialize the TCM RAM with error checking turned on or off, according to the following rules. See c1, Auxiliary Control Register. The error code written to the TCM are valid for the data provided, even if the error checking is turned off.

If the slave port is used, write transactions must be used that write to the TCM memory as follows:

  • If the error scheme is 32-bit ECC, the write transaction must start at a 32-bit aligned addresses and write a continuous block of memory, containing a multiple of 4 bytes. All bytes in the block must be written, that is, have their byte lane strobe asserted.

  • If the error scheme is 64-bit ECC, the write transaction must start at a 64-bit aligned addresses and write a continuous block of memory, containing a multiple of 8 bytes. All bytes in the block must be written, that is, have their byte lane strobe asserted.

If initialization is done by running code on the processor, this is best done by a loop of stores that write to the whole of the TCM memory as follows:

  • If the scheme is 32-bit ECC, use Store Word (STR), Store Two Words (STRD), or Store Multiple Words (STM) instructions to 32-bit aligned addresses.

  • If the scheme is 64-bit ECC, use STRD or STM that has an even number of registers in the register list, with a 64-bit aligned starting address.

Note

You can use the alignment-checking features of the processor to ensure that memory accesses are 32-bit aligned, but there is no checking for 64-bit alignment. If you are using STRD or STM, an alignment fault is generated if the address is not 32-bit aligned. For the same behavior with STR instructions, enable strict-alignment-checking by setting the A-bit in the SCTLR. See c1, System Control Register.

If the error scheme is 64-bit ECC, a simpler way to initialize the TCM is:

  • Ensure error checking is off.

  • Turn on 64-bit store behavior using CP15. See c15, Secondary Auxiliary Control Register.

  • Write to the TCM using any store instructions, or any AXI write transactions. The processor performs read-modify-write accesses to ensure that all writes are to 64-bit aligned quantities, even though error checking is turned off.

Note

You can enable error checking and 64-bit store behavior on a per-TCM interface basis. References in this section, to these controls relate to whichever TCM is being initialized.

Using TCMs from reset

The processor can be pin-configured to enable the TCM interfaces from reset, and to select the address at which each TCM appears from reset. See TCM initialization for more information. This enables you to configure the processor to boot from TCM but, to do this, the TCM must first be preloaded with the boot code. The nCPUHALTm pin can be asserted while the processor is in reset to stop the processor from fetching and executing instructions after coming out of reset. While the processor is halted in this way, the TCMs can be preloaded with the appropriate data. When the nCPUHALTm pin is deasserted, the processor starts fetching instructions from the reset vector address in the normal way.

Note

When nCPUHALTm has been deasserted to start the processor fetching, nCPUHALTm must not be asserted again except when the processor is under processor or power-on reset, that is, nRESETm asserted. The processor does not halt if the nCPUHALTm pin is asserted while the processor is running.

Peripheral Interfaces

The memory regions used by the peripheral interfaces are fixed during integration. Before you access any peripherals that are in those regions, and attached to the peripheral ports, you must enable the peripheral interfaces. The AXI peripheral interface and the AHB peripheral interface can be enabled from reset by tying INITPPXm and INITPPHm HIGH respectively. If they are not enabled at reset your software must enable them by writing to the appropriate CP15 region register. See Peripheral interface region registers. The virtual AXI peripheral interface can only be enabled by software.

Note

The virtual peripheral interface region is a sub-region of the AXI peripheral interface region. If the AXI peripheral interface is enabled, but the virtual AXI peripheral interface is not, then all accesses to this region of memory use the AXI peripheral port. Enabling the virtual AXI peripheral interface affects only the ordering and ID behavior of the transactions, not the physical port that they use.

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