2.1.9. Debug

Each CPU has a CoreSight compliant Advanced Peripheral Bus version 3 (APBv3) debug interface. This permits system access to debug resources, for example, the setting of watchpoints and breakpoints.

The processor provides extensive support for real-time debug and performance profiling.

The following sections give an overview of debug:

System performance monitoring

This is a group of counters that you can configure to monitor the operation of the processor and memory system. For more information, see About the PMU.

ETM interface

The Embedded Trace Macrocell (ETM) interface enables you to connect an external ETM unit to the processor for real-time code tracing of the core in an embedded system.

The ETM interface collects various processor signals and drives these signals from the processor. The interface is unidirectional and runs at the full speed of the processor. The ETM interface connects directly to the external ETM unit without any additional glue logic. You can disable the ETM interface for power saving. For more information, see the CoreSight ETM-R5 Technical Reference Manual.

Real-time debug facilities

Each CPU contains an EmbeddedICE logic unit to provide real-time debug facilities. It has:

  • up to eight breakpoints

  • up to eight watchpoints

  • a Debug Communications Channel (DCC).


The number of breakpoints and watchpoints is configured during implementation, see Configurable options.

The EmbeddedICE logic monitors the internal address and data buses. You access the EmbeddedICE logic through the memory-mapped APB interface.

The processor implements the ARMv7 Debug architecture, including the extensions of the architecture to support CoreSight.

See Chapter 12 Debug for more information on debug.

The EmbeddedICE logic supports two modes of debug operation:

Halt mode

On a debug event, such as a breakpoint or watchpoint, the debug logic stops the processor and forces it into debug state. This enables you to examine the internal state of the processor, and the external state of the system, independently from other system activity. When the debugging process completes, the processor and system state are restored, and normal program execution resumes.

Monitor debug mode

On a debug event, the processor generates a debug exception instead of entering debug state, as in halt mode. The exception entry enables a debug monitor program to debug the processor while enabling critical interrupt service routines to operate on the processor. The debug monitor program can communicate with the debug host over the DCC or any other communications interface in the system.

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