2.1.4. L1 memory system

The processor L1 memory system includes the following features:

For more information of the blocks in the L1 memory system, see:

Instruction and data caches

You can configure the processor to include separate instruction and data caches. The caches have the following features:

  • Support for independent configuration of the instruction and data cache sizes between 4KB and 64KB.

  • Pseudo-random cache replacement policy.

  • 8-word cache line length. Cache lines can be either write-back or write-through, determined by MPU region.

  • Ability to disable each cache independently.

  • Streaming of sequential data from LDM and LDRD operations, and sequential instruction fetches.

  • Critical word first filling of the cache on a cache miss.

  • Implementation of all the cache RAM blocks and the associated tag and valid RAM blocks using standard ASIC RAM compilers.

Memory Protection Unit

An optional MPU provides memory attributes for embedded control applications. You can configure the MPU to have eight or twelve regions, each with a minimum resolution of 32 bytes. MPU regions can overlap, and the highest numbered region has the highest priority.

The MPU checks for protection and memory attributes, and some of these can be passed to an external L2 memory system.

For more information, see Chapter 7 Memory Protection Unit.

TCM interfaces

Because some applications do not cache well, there are two TCM interfaces that permit connection to configurable memory blocks of Tightly-Coupled Memory (ATCM and BTCM). These ensure high-speed access to code or data. As an option, the BTCM can have two memory ports for increased bandwidth.

An ATCM typically holds interrupt or exception code that must be accessed at high speed, without any potential delay resulting from a cache miss.

A BTCM typically holds a block of data for intensive processing, such as audio or video processing.

The TCMs are external to the processor. This provides flexibility in optimizing the TCM subsystem for performance, power, and RAM type. The INITRAMAm and INITRAMBm pins enable booting from the ATCM or BTCM, respectively. Both the ATCM and BTCM support wait states.

For more information, see Chapter 8 Level One Memory System.

Error correction and detection

To increase the tolerance of the system to soft memory faults, you can configure the caches for either:

  • parity generation and error correction/detection

  • ECC code generation, single-bit error correction, and two-bit error detection.

Similarly, you can configure the TCM interfaces for ECC code generation, single-bit error correction, and two-bit error detection.

For more information, see Chapter 8 Level One Memory System.

Copyright © 2010-2011 ARM. All rights reserved.ARM DDI 0460C
Non-ConfidentialID021511