2.1.5. L2 AXI interfaces

The L2 AXI interfaces enable the L1 memory system to have access to peripherals and to external memory using an AXI master and AXI slave port and the peripheral ports. See Chapter 9 Level Two Interface for more information.

AXI master interface

The AXI master interface provides a high bandwidth interface to second level caches, on-chip RAM, peripherals, and interfaces to external memory. It consists of a single AXI port with a 64-bit read channel and a 64-bit write channel for instruction and data fetches.

The AXI master can run at the same frequency as the processor, or at a lower synchronous frequency. If asynchronous clocking is required an external asynchronous AXI slice is required.

AXI slave interface

The AXI slave interface enables AXI masters, including the AXI master port of the processor, to access data and instruction cache RAMs and TCMs on the AXI system bus. You can use this for DMA into and out of the TCM RAMs and for software test of the TCM and cache RAMs.

The slave interface can run at the same frequency as the processor or at a lower, synchronous frequency. If asynchronous clocking is required an external asynchronous AXI slice is required.

Bits in the Auxiliary Control Register and Slave Port Control Register can control access to the AXI slave. Access to the TCM RAMs can be granted to any master, to only privileged masters, or completely disabled. Access to the cache RAMs can be separately controlled in a similar way.

Peripheral interfaces

The peripheral interfaces provide low latency interfaces to on-chip RAM and peripherals for non-cached data accesses only. They consist of a single 32-bit AXI port, accessed through two interfaces, and a single 32-bit AHB port accessed through a single interface.

The peripheral interfaces can run at the same frequency as the processor, or at a lower synchronous frequency. If asynchronous clocking is required, an external asynchronous AXI slice and asynchronous AHB bridge is required.

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