7.3. Region attributes

Each region has a number of attributes associated with it. These control how a memory access is performed when the processor accesses an address that falls within a given region. The attributes are:

The Region Access Control Registers use five bits to encode the memory region type. These are the TEX[2:0], C and B bits. Table 4.36 shows the mapping of these bits to memory region attributes.


In earlier versions of the architecture, the TEX, C, and B bits were known as the Type Extension, Cacheable and Bufferable bits. These names no longer adequately describe the function of the B, C, and TEX bits.

All memory attributes that are Cacheable, write-back or write-through, are also implicitly read-allocate. Table 4.36 shows which attributes are write-allocate.

In addition, the Region Access Control Registers contain the shared bit, S. This bit only applies to Normal memory, and determines whether the memory region is Shared (1) or Non-shared (0).

When the processor performs a memory access through its AXI bus master interface:

For the encodings, see Table 9.2.

Similarly, for memory accesses performed through the AXI peripheral port, the Outer attributes are indicated on the A*CACHEPm signals.

For more information on region attributes, see the ARM Architecture Reference Manual.

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