1.5. Configurable options

Table 1.1 shows the features of the processor that can be configured using either build-configuration or pin-configuration. See Product documentation, design flow, and architecture for information about configuration of the processor. Many of these features, if included, can also be enabled and disabled during software configuration. In a twin-CPU configuration, some of the options can be configured separately for each CPU while for other options both CPUs take the same value. Options that permit independent configuration are highlighted with footnotes in Table 1.1 and Table 1.2.

Table 1.1. Configurable options

FeatureOptionsSub-optionsBuild-configuration or pin-configuration
Number of CPUs[a]Single-CPU (no redundancy)-Build
Redundant CPU-Build
Twin-CPU (no redundancy)-Build
Split/Lock

Safety-mode (redundancy)

Performance-mode (twin CPU)

Build and pin
Instruction cacheNo I-Cache[b]-Build
I-Cache included[b]

No error checking

Parity error checking

64-bit ECC error checking

Build

4KB (4x1KB ways)[b]

8KB (4x2KB ways)[b]

16KB (4x4KB ways)[b]

32KB (4x8KB ways)[b]

64KB (4x16KB ways)[b]

Build
Data cacheNo D-Cache[b]-Build
D-Cache included[b]

No error checking[b]

Parity error checking

32-bit ECC error checking

Build

4KB (4x1KB ways)[b]

8KB (4x2KB ways)[b]

16KB (4x4KB ways)[b]

32KB (4x8KB ways)[b]

64KB (4x16KB ways)[b]

Build
ATCMNo ATCM ports-Build and pin
One ATCM port

No error checking

32-bit ECC error checking

64-bit ECC error checking

Build
4KB, 8KB, 16KB, 32KB, 64KB, 128KB, 256KB, 512KB, 1MB, 2MB, 4MB, or 8MB[b]Pin
BTCMNo BTCM ports-Build and pin
One BTCM port (B0TCM)[b]

No error checking

32-bit ECC error checking

64-bit ECC error checking

Build and pin[c]
4KB, 8KB, 16KB, 32KB, 64KB, 128KB, 256KB, 512KB, 1MB, 2MB, 4MB, or 8MB[b]Pin
Two BTCM ports (B0TCM and B1TCM)[b]

No error checking

32-bit ECC error checking

64-bit ECC error checking

Build and pin[c]
2x2KB, 2x4KB, 2x8KB, 2x16KB, 2x32KB, 2x64KB, 2x128KB, 2x256KB, 2x512KB, 2x1MB, 2x2MB, or 2x4MB[b]Pin

Interleaved on 64-bit granularity in memory[b]

Adjacent in memory[b]

Pin
Instruction endiannessLittle-endian-Build
Pin-configured

Little-endian

Big-endian

Pin
Floating point (VFP)No FPU[b]-Build
FPU included[b][d]

Full implementation

Single-precision only

MPUNo MPU[b]-Build
MPU included[b]

12 MPU regions[b]

16 MPU regions[b]

Build
TCM bus parityNo TCM address and control bus parity-Build
TCM address and control bus parity generated-
AXI bus ECC/parity on AXI-master, AXI-slave (if included) and ACP (if included)No AXI bus ECC/parity-Build
AXI bus ECC/parity generated/ checked-
Bus ECC/parity on AXI peripheral port and AHB peripheral port (if included)No peripheral port bus ECC/parity-Build
Peripheral port bus ECC/parity generated/checked-
Breakpoints2-8 breakpoint register pairs-Build
Watchpoints1-8 watchpoint registers-Build
ATCM at resetDisabled[b]-Pin
Enabled[b] [e]

Base address 0x0[b]

Base address configured[b]

Build and pin
BTCM at resetDisabled[b]-Pin
Enabled[b][e]

Base address configured[b]

Base address 0x0[b][f]

Build and pin
Peripheral ID RevAnd fieldAny 4-bit value-Build
AXI slave interfaceNo AXI-slave[b]-Build
AXI-slave included[b]-
TCM Hard Error CacheNo TCM Hard Error Cache-Build
TCM Hard Error Cache included [g]-
Non-Maskable FIQ InterruptDisabled (FIQ can be masked by software)-Pin
Enabled-
Parity type[h]Odd parity-Pin
Even parity-
AXI coherency port (ACP)No ACP-Build
ACP included-
AHB peripheral portAXI peripheral port only-Build
AXI and AHB peripheral portsAHB peripheral port region size: 4KB, 8KB, 16KB, 32KB, 64KB, 128KB, 256KB, 512KB, 1MB, 2MB, 4MB, or 8MB. 16MB, 32MB, 64MB, 128MB, 256MB, 512MB, 1GB, 2GB, 4GB[b]Build and pin
AHB peripheral port base address: any size-aligned address[b]
AXI peripheral interface region size4KB, 8KB, 16KB, 32KB, 64KB, 128KB, 256KB, 512KB, 1MB, 2MB, 4MB, or 8MB. 16MB, 32MB, 64MB, 128MB, 256MB, 512MB, 1GB, 2GB, 4GB[b]-Pin
AXI peripheral interface base addressAny size-aligned address[b]-Pin
Virtual AXI peripheral interface region size4KB, 8KB, 16KB, 32KB, 64KB, 128KB, 256KB, 512KB, 1MB, 2MB, 4MB, or 8MB. 16MB, 32MB, 64MB, 128MB, 256MB, 512MB, 1GB, 2GB, 4GB[b]-Pin
Virtual AXI peripheral interface base addressAny size-aligned address[b]-Pin
Cortex-R5 group IDAny 4-bit value-Pin

[a] See CPU configurations for more information.

[b] This option, or some aspects of it, can be configured separately for each CPU on a twin-CPU build.

[c] The error scheme is a build option only. The number of BTCM ports (none, one, two) is set by both build and pin configuration.

[d] Only available with the Cortex-R5F processor.

[e] Only if the relevant TCM port(s) are included.

[f] The BTCM base address must be size aligned, to the total size of B0TCM + B1TCM.

[g] Only if at least one TCM port is included and uses ECC error checking.

[h] Only relevant if one of the caches includes parity checking, or AXI bus ECC or TCM bus parity is included.


Table 1.2 describes the various features that can be pin-configured to be either enabled or disabled at reset. It also shows which CP15 register field provides software configuration of the feature when the processor is out of reset. All of these fields exist in either the SCTLR, or one of the auxiliary control registers.

Table 1.2. Configurable options at reset

FeatureOptionsRegister field
Exception endiannessLittle-endian/big-endian data for exception handlingSCTLR.EE
Exception stateARM/Thumb state for exception handlingSCTLR.TE
Exception vector tableBase address for exception vectors: 0x00000000/0xFFFF0000[a]SCTLR.V
TCM error checkingATCM ECC check enable[a][b]ACTLR.ATCMPCEN
BTCM ECC check enabled, for B0TCM and B1TCM together[a][b]ACTLR.B0TCMPCEN/ ACTLR.B1TCMPCEN
TCM external errorsATCM external error enable[a]ACTLR.ATCMECEN
BTCM external error enable, for B0TCM and B1TCM independentlyACTLR.B0TCMECEN/ ACTLR.B1TCMECEN
TCM load/store-64 (read-modify-write) behaviorATCM load/store-64 enable[a][c]ACTLR2.ATCMRMW
BTCM load/store-64 enable[a][c]ACTLR2.BTCMRMW
AXI peripheral interfaceRegion enable[a]PPX.En
AHB peripheral interface[d] Region enable[a]PPH.En

[a] This can be configured separately for each CPU on a twin-CPU build.

[b] Can only be enabled if the appropriate TCM is configured with the appropriate error checking scheme, and the appropriate number of ports

[c] Can only be enabled if the appropriate TCM is not configured with 32-bit ECC.

[d] Can only be enabled if the AHB peripheral port is included.


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