9.3. AXI master interface transfers

The processor conforms to the AXI3 specification, but it does not generate all the AXI transaction types that the specification permits. This section describes the types of AXI transaction that the Cortex-R5 AXI master does not generate. If you are designing an AXI slave to work only with the Cortex-R5 processor, and there are no other AXI masters in your system, you can take advantage of these restrictions and the interface attributes, described in Table 9.1, to simplify the slave.

This section also contains tables that show some examples of the types of AXI burst that the processor generates. However, because a particular type of transaction is not shown here does not mean that the processor does not generate such a transaction.

Note

An AXI slave device connected to the Cortex-R5 AXI master port must be capable of handling every kind of transaction permitted by the AXI specification, except where there is an explicit statement in this chapter that such a transaction is not generated. You must not infer any additional restrictions from the example tables given. Restrictions described here apply to the r0p0 to r1p1revisions of the processor, but might not be true for future revisions.

Load and store instructions to Non-cacheable memory might not result in an AXI transfer because the data might either be retrieved from, or merged into the internal store data buffers. The exceptions to this are loads or stores to Strongly Ordered or Device memory. These always result in AXI transfers. See Strongly Ordered and Device transactions.

Restrictions on AXI transfers describes restrictions on the type of transfers that the Cortex-R5 AXI master interface generates. If a CPUm exists and is powered up, the buffered write response and read data channel ready signals, BREADYMm and RREADYMm, are always asserted. They are, however, deasserted when the CPU enters Dormant or Shutdown mode. You must not make any other assumptions about the AXI handshaking signals, except that they conform to the AMBA AXI Protocol Specification.

The following sections give examples of transfers generated by the AXI master interface:

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