8.4.3. TCM internal error detection and correction

Each TCM interface can be configured with either 32-bit ECC, or 64-bit ECC error schemes. Both the BTCM ports must have the same error scheme. This section describes these error schemes.

If a TCM interface has been built with either 32-bit or 64-bit ECC error checking, you can enable this by setting the appropriate bits in the Auxiliary Control Register. See c1, Auxiliary Control Register. On the BTCM interface, ECC checking can only be enabled for both ports or neither port. You can pin-configure the processor to set the enable bits and therefore enable ECC checking on reset, by tying off the PARECCENRAMm input as required.

When a fatal error, that is, a 2-bit ECC error, is detected on a TCM read, an error is generated. Instruction and data reads generate the appropriate type of synchronous abort, and the AXI-slave interface returns a SLVERR response to the AXI system.

When a correctable error, that is, a 1-bit ECC error, is detected on a TCM read made by the AXI-slave interface, the processor corrects the data inline before returning to the system.

When a correctable ECC error is detected on a TCM read made by the instruction-side or data-side, the processor normally generates the correct data and writes it back to the TCM. In the meantime, the processor retries the read to fetch the correct instruction or data. By setting the appropriate bits in the Secondary Auxiliary Control Register, you can disable this behavior. See c15, Secondary Auxiliary Control Register. Instead of correcting the error in the TCM, the processor generates the appropriate type of synchronous abort.

All ECC code generation and ECC checking must be performed on a complete data chunk, either 32-bits or 64-bits depending on the configuration. If a read access smaller than the data chunk is required, the whole chunk is read. If a write smaller than the data chunk is required, the processor must perform read-modify-write to generate the correct data and ECC code, but it only does this when ECC error checking is enabled. The data read as part of the read-modify-write sequence is checked for ECC errors, and the errors are handled in the same way as for any other TCM read. The ECC code is generated and written to the TCM for every write, regardless of whether error checking is enabled or not, but the code is only correct if the write was of a complete data chunk or if the processor performed read-modify-write to generate the complete data chunk. All data and instruction aborts generated by the ECC logic are indicated in the appropriate FSR as being a synchronous parity error.

Copyright © 2010-2011 ARM. All rights reserved.ARM DDI 0460C