8.4.7.  External TCM errors

Each TCM port has a number of features that support the integration of a TCM RAM with an error checking scheme implemented in the RAM controller logic outside of the processor, that is, by the integrator.

Errors can be signaled to each TCM port if the external error checking scheme detects one and, if enabled, the processor generates an instruction or data abort or an AXI error response as appropriate. On a TCM read from either the instruction-side or data-side, the TCM controller can indicate that the read must be retried instead of generating an abort.

You can enable external errors for each TCM port individually by setting the appropriate bits in the Auxiliary Control Register. See c1, Auxiliary Control Register. If external errors are not enabled for a TCM port, the processor ignores any error signaled on that port. You can pin-configure the processor to set the enable bits, and therefore enable external error checking on reset, by tying off the ERRENRAMm input as required.

In addition, an external error detection scheme might require that data is read and written in particular sized chunks. The load/store-64 feature, when enabled for a particular TCM interface, causes all loads and stores to the TCM ports to be of 64-bits of data. This feature is also known as Read-Modify-Write (RMW), because it causes the processor to generate read-modify-write sequences for any store of less than 64-bits. You can enable RMW behavior for each TCM interface individually by setting the appropriate bits in the Secondary Auxiliary Control Register. See c1, Auxiliary Control Register. You can pin-configure the processor to set the enable bits and therefore RMW behavior on reset, by tying off the RMWENRAMm input as required.

Note

The load/store-64 feature is not available on any TCM interface that has been configured with 32-bit ECC.

The error inputs on each TCM port can also be used to signal other types of error, for example, when an address accessed is out of range for the RAM attached to the TCM port. Errors signaled on writes from the data-side generate an asynchronous abort. All other aborts generated by external errors are synchronous. The type of abort is shown in the appropriate FSR as either synchronous or asynchronous parity error.

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