12.9.1. Cache pollution in debug state

If bit [0] of the Debug State Cache Control Register (DBGDSCCR) is set to 0 while the processor is in debug state, then the L1 data cache does not perform any line fill.


No special feature is required to prevent L1 instruction cache pollution because instruction side fetches cannot occur while in debug state.

Copyright © 2010-2011 ARM. All rights reserved.ARM DDI 0460C