12.10.2. Miscellaneous debug signals

This section describes the miscellaneous debug signals.

EDBGRQm

This signal generates a halting debug event, that is, it requests the CPU to enter debug state. When this occurs, the DBGDSCR[5:2] method-of-debug entry bits are set to b0100. When EDBGRQm is asserted, it must be held until DBGACKm is asserted. Failure to do so leads to Unpredictable behavior of the processor.

DBGACKm

The CPU asserts DBGACKm to indicate that the system has entered debug state. It serves as a handshake for the EDBGRQm signal. The DBGACKm signal is also driven HIGH when the debugger sets the DBGDSCR[10] DbgAck bit to 1.

DBGNOPWRDWN

The CPU asserts DBGNOPWRDWN when bit [0] of the Device Power down and Reset Control Register is 1 in either CPU. The processor power controller must work in Emulate mode when this signal is HIGH.

DBGROMADDR

The DBGROMADDR signal specifies bits [31:12] of the debug ROM physical address. This is a configuration input and must be tied off or only change while the processor is in reset. In a system with multiple debug ROMs, this address must be tied off to point to the top-level ROM address.

DBGROMADDRV is the valid signal for DBGROMADDR. If the address cannot be determined, DBGROMADDR must be tied off to zero and DBGROMADDRV must be tied LOW. The value of these signals can be read from the Debug ROM Address Register (DBGDRAR).

DBGSELFADDRm

The DBGSELFADDRm signal specifies bits [31:12] of the offset from the debug ROM physical address to the physical address where the CPU APB port is mapped to the base of the 4KB debug register map. This is a configuration input and must be tied off or only change while the CPU is in reset.

DBGSELFADDRVm is the valid signal for DBGSELFADDRm. If the offset cannot be determined, DBGSELFADDRm must be tied off to zero and DBGSELFADDRVm must be tied LOW. The value of these signals can be read from the Debug Self Address Register (DSAR).

DBGRESTARTm

The DBGRESTARTm signal is used to bring the CPU out of debug halt state. The CPU acknowledges DBGRESTARTm by asserting DBGRESTARTEDm, and then starts fetching instructions when DBGRESTARTm is deasserted.

DBGRESTARTEDm

The CPU asserts DBGRESTARTEDm in response to a DBGRESTARTm request, when it is ready to exit debug halt state and return to normal run state.

DBGTRIGGERm

The CPU asserts DBGTRIGGERm to indicate that the system has accepted a debug request and attempts to enter debug state. It is not a handshake for the EDBGRQm signal. If DBGACKm does not go HIGH following DBGTRIGGERm, the memory system has stopped responding and the CPU has not entered debug state.

Table A.22 shows the debug miscellaneous signals.

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