Cortex-R5 and Cortex-R5F Technical Reference Manual: 12.4.5. Data Transfer Register

12.4.5. Data Transfer Register

The DTR consists of two separate physical registers:

the DBGDTRRX (Read Data Transfer Register)
the DBGDTRTX (Write Data Transfer Register).

The register accessed is dependent on the instruction used:

writes, MCR and LDC instructions, access the DBGDTRTX
reads, MRC and STC instructions, access the DBGDTRRX.

Note

Read and write are used with respect to the processor.

For information on the use of these registers with the TXfull flag and RXfull flag, see Debug communications channel. The Data Transfer Register, bits [31:0] contain the data to be transferred.

Table 12.10 shows how the bit values correspond with the DBGDTRRX and DBGDTRTX functions.

Table 12.10. Data Transfer Register bit assignments

Bits	Name	Function
[31:0]	Data	Reads the Data Transfer Register. This is read-only for the CP14 interface. Note Reads of the DBGDTRRXint through the coprocessor interface cause the TXfull flag to be cleared. However, reads of the DBGDTRRXext through the APB port do not affect this flag.
[31:0]	Data	Writes the Data Transfer Register. This is write-only for the CP14 interface. Note Writes to the DBGDTRTXint through the coprocessor interface cause the RXfull flag to be set. However, writes to the DBGDTRTXext through the APB port do not affect this flag.

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