12.9.2. Cache coherency in debug state

The debugger can update memory while in debug state:

The debugger can maintain cache coherency in both these situations with the following features:


The processor can normally execute CP15 instruction cache invalidate all operation or CP15 instruction cache invalidate line operation only in Privileged mode. However, in debug state the processor can execute these instructions even when invasive debug is not permitted in Privileged mode. This exception to the rule enables the debugger to maintain coherency.

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