12.6.2. Halting debug event

The debugger or the system can cause the processor to enter into debug state by triggering any of the following halting debug events:

When EDBGRQm is asserted while DBGENm is HIGH, the device asserting this signal must hold it until the processor enters debug state, that is, until DBGACKm is asserted. The state of the processor pipeline determines how long this takes. If the request is not held in this way, the behavior of the processor is Unpredictable. For DBGDRCR[0] halting debug events, the processor records them internally until it is in a state and mode so that they can be taken.

Copyright © 2010-2011 ARM. All rights reserved.ARM DDI 0460C
Non-ConfidentialID021511