12.11.4. Debug state entry

On entry to debug state, the debugger can read the processor state, including all registers and the PC, and determine the cause of the exception from the DBGDSCR method-of-entry bits.

Example 12.11 shows the code for entry to debug state.

Example 12.11. Entering debug state

OnEntryToDebugState(PROCESSOR_STATE *state)
{
    // Step 1. Read the DBGDSCR to determine the cause of debug entry.
    state->dbgdscr := ReadDebugRegister(34);
    // Step 2. Issue a DataSynchronizationBarrier instruction if required;
    // this is not required by the Cortex-R5 processor but is required for ARMv7
    // debug.
    if ((state->dbgdscr & (1<<19)) == 0)
    {
        ExecuteARMInstruction(0xE57FF040)
        // Step 3. Poll the DBGDSCR for DBGDSCR[19] to be set.
        repeat
        {
                dbgdscr := ReadDebugRegister(34);
        }
        until (dbgdscr & (1<<19));
    }
    // Step 4. Read the entire processor state. The function ReadAllRegisters
    //    reads all general-purpose registers for all processor modes, and saves
    //    the data in “state”.
    ReadAllRegisters(state);
    // Step 5. Based on the CPSR (processor state), determine the actual restart
    //    address
    if (state->cpsr & (1<<5);
    {
        // Thumb state
        state->pc := state->pc - 4;
    }
    else
    {
        // ARM state
        state->pc := state->pc - 8;
    }
    // Step 6. If the method of entry was Watchpoint Occurred, read the DBGWFAR
    // register
    method_of_debug_entry := ((state->dbgdscr >> 2) & 0xF;
    if (method_of_debug_entry == 2 || method_of_debug_entry == 10)
    {
        state->dbgwfar := ReadDebugRegister(6);
    }
}

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