12.4.4. CP14 c1, Debug Status and Control Register

The DBGDSCR Register characteristics are:

Purpose

Contains status and control information about the debug unit.

Usage constraints
Configurations

Available in all processor configurations.

Attributes

Figure 12.5 shows the bit assignments.

Figure 12.5. DBGDSCR Register bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 12.9 shows the bit assignments.

Table 12.9. DBGDSCR Register bit assignments

BitsNameFunction

[31]

-

RAZ on reads, SBZP on writes.

[30]

RXfull

The RXfull flag:

0 = Read-DTR, DBGDTRRX, empty, reset value

1 = Read-DTR, DBGDTRRX, full.

When set, this flag indicates to the processor that there is data available to read at the DBGDTRRXint. It is automatically set on writes to the DBGDTRRXext by the debugger, and is cleared when the processor reads the CP14 DTR. If the flag is not set, the DBGDTRRXint returns an Unpredictable value.

[29]

TXfull

The TXfull flag:

0 = Write-DTR, DBGDTRTX, empty, reset value

1 = Write-DTR, DBGDTRTX, full.

When clear, this flag indicates to the processor that the DBGDTRTXint is ready to receive data. It is automatically cleared on reads of the DBGDTRTXext by the debugger, and is set when the processor writes to the CP14 DTR. If this bit is set and the processor attempts to write to the DBGDTRTXint, the register contents are overwritten and the TXfull flag remains set.

[28:26]

-

RAZ on reads, SBZP on writes.

[25]

PipeAdv

Sticky pipeline advance read-only bit. This bit enables the debugger to detect whether the processor is idle. In some situations, this might mean that the system bus port is deadlocked. This bit is set to 1 when the processor pipeline retires one instruction. It is cleared by a write to DBGDRCR[3].

0 = no instruction has completed execution since the last time this bit was cleared

1 = an instruction has completed execution since the last time this bit was cleared.

[24]

InstrCompl_l

Instruction complete read-only bit. This flag determines whether the processor has completed execution of an instruction issued through the APB port.

0 = processor is executing an instruction fetched from the DBGITR Register

1 = processor is not executing an instruction fetched from the DBGITR Register.

When the APB port reads the DBGDSCR and this bit is clear, then a subsequent write to the DBGITR Register is ignored unless DBGDSCR[21:20] is not equal to 0. If DBGDSCR[21:20] is not equal to 0, the DBGITR write stalls until the processor completes execution of the current instruction. If the processor is not in debug state, then the value read for this flag is Unpredictable. The flag is set to 1 on entry to debug state.

[23:22]

-

RAZ on reads, SBZP on writes.

[21:20]

ExtDCCmode

DTR access mode. You can use this field to optimize DTR traffic between a debugger and the processor.

b00 = Non-blocking mode, this is the reset value

b01 = Stall mode

b10 = Fast mode

b11 = Reserved.

Note

  • This field only affects the behavior of DBGDSCRext, DBGDTRRXext, DBGDTRTXext, and DBGITR accesses through the APB port, and not through CP14 debug instructions.

  • Non-blocking mode is the default setting. Improper use of the other modes might result in the debug access bus becoming deadlocked.

See DTR access mode for more information.

[19]

ADAdiscard

The Asynchronous Aborts Discarded bit is set when the processor is in debug state and is cleared on exit from debug state. While this bit is set, the processor does not take asynchronous Data Aborts, instead, the sticky asynchronous Data Abort bit is set to 1.

0 = do not discard asynchronous Data Aborts

1 = discard asynchronous Data Aborts and set ADABORT_I.

[18]NS RAZ on reads, SBZP on writes.
[17]SPNIDdis This bit is the inverse of bit [6] of the DBGAUTHSTATUS, see Authentication Status Register.
[17]SPIDdis This bit is the inverse of bit [4] of the DBGAUTHSTATUS, see Authentication Status Register.

[15]

MDBGen

The Monitor debug-mode enable bit:

0 = Monitor debug-mode disabled, this is the reset value

1 = Monitor debug-mode enabled.

If Halting debug-mode is enabled through bit [14], then the processor is in Halting debug-mode regardless of the value of bit [15]. If the external interface input DBGENm is LOW, this bit reads as 0. The programmed value is masked until DBGENm is HIGH, and at that time the read value reverts to the programmed value.

[14]HDBGen

The Halting debug-mode enable bit:

0 = Halting debug-mode disabled, this is the reset value

1 = Halting debug-mode enabled.

If the external interface input DBGENm is LOW, this bit reads as 0. The programmed value is masked until DBGENm is HIGH, and at that time the read value reverts to the programmed value.

[13]

ITRen

Execute ARM instruction enable bit:

0 = disabled, this is the reset value

1 = enabled.

If this bit is set and an DBGITR write succeeds, the processor fetches an instruction from the DBGITR for execution. If this bit is set to 1 when the processor is not in debug state, the behavior of the processor is Unpredictable.

[12]

UDCCdis

CP14 debug user access disable control bit:

0 = CP14 debug user access enable, this is the reset value

1 = CP14 debug user access disable.

If this bit is set and a User mode process attempts to access any CP14 debug registers, an Undefined Instruction exception is taken.

[11]

IntDis

Interrupts disable bit:

0 = interrupts enabled, this is the reset value

1 = interrupts disabled.

If this bit is set, the nIRQm and nFIQm input signals are inhibited. The external debugger can optionally use this bit to execute pieces of code in normal state as part of the debugging process and avoid having an interrupt taking control of the program flow.

[10]

DbgAck

Force Debug Acknowledge bit. If this bit is set to 1, the DBGACKm output signal is forced HIGH, regardless of the processor state. The external debugger can optionally use this bit to execute pieces of code in normal state as part of the debugging process for the system to behave as if the processor is in debug state. Some systems rely on DBGACKm to determine whether data accesses are application or debugger generated. This bit is 0 on reset.

[9]

-

RAZ on reads, SBZP on writes.

[8]

UND_I

Sticky Undefined bit:

0 = no Undefined Instruction exception occurred in debug state since the last time this bit was cleared

1 = an Undefined Instruction exception occurred while in debug state since the last time this bit was cleared.

This flag detects Undefined Instruction exceptions generated by instructions issued to the processor through the DBGITR. This bit is set to 1 when an Undefined Instruction exception occurs while the processor is in debug state and is cleared by writing a 1 to DBGDRCR[2].

[7]

ADABORT_l

Sticky asynchronous Data Abort bit:

0 = no asynchronous Data Aborts occurred since the last time this bit was cleared

1 = an asynchronous Data Abort occurred since the last time this bit was cleared.

This flag detects asynchronous Data Aborts triggered by instructions issued to the processor through the DBGITR. This bit is set to 1 when an asynchronous Data Abort occurs while the processor is in debug state and is cleared by writing a 1 to DBGDRCR[2].

[6]

SDABORT_I

Sticky synchronous Data Abort bit:

0 = no synchronous Data Abort occurred since the last time this bit was cleared

1 = a synchronous Data Abort occurred since the last time this bit was cleared.

This flag detects synchronous Data Aborts generated by instructions issued to the processor through the DBGITR. This bit is set to 1 when a synchronous Data Abort occurs while the processor is in debug state and is cleared by writing to the DBGDRCR[2].

[5:2]

MOE

Method of entry bits:

b0000 = a DBGDRCR[0] halting debug event occurred

b0001 = a breakpoint occurred

b0100 = an EDBGRQm halting debug event occurred

b0011 = a BKPT instruction occurred

b1010 = a synchronous watchpoint occurred

others = reserved.

These bits are set to indicate any of:

  • the cause of a debug exception

  • the cause for entering debug state.

A Prefetch Abort or Data Abort handler must check the value of the CP15 Fault Status Register to determine whether a debug exception occurred and then use these bits to determine the specific debug event.

[1][a]

RESTARTED

CPU restarted bit:

0 = The processor is exiting debug state.

1 = The processor has exited debug state. This is the reset value.

The debugger can poll this bit to determine when the processor responds to a request to leave debug state.

[0][a]

HALTED

CPU halted bit:

0 = The processor is in normal state. This is the reset value.

1 = The processor is in debug state.

The debugger can poll this bit to determine when the processor has entered debug state.

[a] These bits always reflect the status of the processor, therefore they only have a reset value if the particular reset event affects the processor. For example, a PRESETDBGmn event leaves these bits unchanged and a processor reset event such as nSYSPORESET sets DBGDSCR[18] to a 0 and DBGDSCR[1:0] to 10.


To use the DBGDSCR, read or write CP14 c1 with:

MRC p14, 0, <Rd>, c0, c1, 0			 ; Read DBGDSCR
MCR p14, 0, <Rd>, c0, c1, 0			 ; Write DBGDSCR

DTR access mode

You can use the ExtDCCmode field to optimize data transfer between a debugger and the processor.

The DCC access mode can be one of the following:

  • Nonblocking. This is the default mode.

  • Stall.

  • Fast.

In Non-blocking mode, reads from DBGDTRTXext and writes to DBGDTRRXext and DBGITR are ignored if the appropriate latched ready flag is not in the ready state. These latched flags are updated on DBGDSCR reads. The following applies:

  • writes to DBGDTRRXext are ignored if RXfull_l is set to b1

  • reads from DBGDTRTXext are ignored, and return an Unpredictable value, if TXfull_l is set to b0

  • writes to DBGITR are ignored if InstrCompl_l is set to b0

  • following a successful write to DBGDTRRXext, RXfull and RXfull_l are set to b1

  • following a successful read from DBGDTRTXext, TXfull and TXfull_l are cleared to b0

  • following a successful write to DBGITR, the internal flags InstrCompl and InstrCompl_l are cleared to b0.

Debuggers accessing these registers must first read DBGDSCRext. This has the side-effect of copying RXfull and TXfull to RXfull_l and TXfull_l. The debugger must then:

  • write to the DBGDTRRXext if the RXfull flag was b0 (RXfull_l is b0)

  • read from the DBGDTRTXext if the TXfull flag was b1 (TXfull_l is b1)

  • write to the DBGITR if the InstrCompl_l flag was b1.

However, debuggers can issue both actions together and later determine from the read DBGDSCR value whether the operations were successful.

In Stall mode, the APB accesses to DBGDTRRXext, DBGDTRTXext, and DBGITR stall under the following conditions:

  • writes to DBGDTRRXext are stalled until RXfull is cleared

  • writes to DBGITR are stalled until InstrCompl is set

  • reads from DBGDTRTXext are stalled until TXfull is set.

Fast mode is similar to Stall mode except that in Fast mode, the processor fetches an instruction from the DBGITR when a DBGDTRRXext write or DBGDTRTXext read succeeds. In Stall mode and Nonblocking mode, the processor fetches an instruction from the DBGITR when a DBGITR write succeeds.

Copyright © 2010-2011 ARM. All rights reserved.ARM DDI 0460C
Non-ConfidentialID021511