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Interrupt handling in the processor is compatible with previous ARM architectures, but has several additional features to improve interrupt performance for real-time applications.
The core has a dedicated port that enables an external interrupt controller, such as the ARM PrimeCell Vectored Interrupt Controller (VIC), to supply a vector address along with an Interrupt Request (IRQ) signal. This provides faster interrupt entry, but you can disable it for compatibility with earlier interrupt controllers.
If you do not have a VIC in your design, you must ensure the nIRQm and nFIQm signals are asserted, held LOW, and remain LOW until the exception handler clears them.
On receipt of an interrupt, the processor abandons any pending
restartable memory operations. Restartable memory operations are
the multiword transfer instructions LDM, LDRD, STRD, STM, PUSH, and POP that
can access Normal memory.
To minimize the interrupt latency, ARM recommends that you do not perform:
multiple accesses to areas of memory marked as Device or Strongly Ordered
SWP operations to slow areas of memory.
The ARMv7-R architecture contains exception processing instructions to reduce interrupt handler entry and exit time:
Save return state to a specified stack frame.
Return from exception using data from the stack.
Change processor state, such as interrupt mask setting and clearing, and mode changes.
| Copyright © 2010-2011 ARM. All rights reserved. | ARM DDI 0460C |
| Non-Confidential | ID021511 |
| PDF version | |
| Home > Functional Description > About the functions > Interrupt handling |