12.8.9. Effects of debug events on processor registers

On entry to debug state, the processor does not update any general-purpose or program status register. This includes the SPSR_abt and R14_abt registers. In addition, the processor does not update any coprocessor registers, including the CP15 IFSR, DFSR, DFAR, or IFAR registers, except for CP14 DBGDSCR[5:2] method-of-entry bits. These bits indicate the type of debug event that caused the entry into debug state.


On entry to debug state because of a watchpoint debug event, the processor updates the DBGWFAR register with the address of the instruction accessing the watchpointed address plus:

  • + 8 in ARM state

  • + 4 in Thumb state.

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